can we neglect clearance violation error between a via and unconnected pad(s).
Probably your use case can be covered with some custom rule, but there’s no condition for “unconnected pad”. You have to describe the situation from wider viewpoint – why you want to do that – and maybe we can help.
It is a multilayer board, and this particular area is cluttered with tracks and vias on all layers. This position provides acceptable clearances except for the unconnected pins exceptions.
So you want to limit the rule to certain pads of a certain footprint? I can see two options. Both involve writing Custom Rules.
- Add a rule area and use “A.insideArea()” (or “A.intersectsArea()” or A.enclosedByArea() in case of v7-rc). The rule area can be added to the footprint or to the board.
- Add the wanted pads to a named group in the footprint. Use “A.isMemberOf()”.
For example (not tested):
(version 1)
(rule viapadclearance
(condition "A.memberOf('myPadGroupName') && B.Type == 'Via' ")
(constraint clearance(min 0.1mm)))
You probably have to take care that the footprint or the pads don’t define their own clearance.
The question is can the manufacturer who set the capabilities in the first place cope with this DRC error, so I would safely ignore it.
A question only the boardhouse can answer …
Maybe I misread you, but KiCad’s constraints are not set by any manufacturer. You have to configure them by yourself to match the boardhouse’s capabilities.
Crystal clear, my board setup constraints are configured in Kicad according to the manufacturer capabilities. I’ll refer to them with my question. Thank you all for your help.
The manufacturer will complain and let you know that they cannot guarantee that the via will not be shorted to the pad(s). Their default proposed solution will probably be to cut a bite out of the via’s pad that is at the minimum clearance diameter from the BGA pad. This might not be possible in your example because the clearance rule you’ve input will result in that clipping the barrel of the via, not just the pad.
Your screenshot is too cropped to tell whether or not there are other reasons you can’t do this, but generally I would first try to offset the GND via in the Y axis to reduce the severity of this problem (or maybe even eliminate it)
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I’ll come back with the manufacturer feedback as soon as I get it.
Maybe there could be an intermediate solution, wherein PCB identifies all copper “islands” without a specified net, then makes a decision:
A) belonging to a footprint: assign a unique net name & enforce all DRC rules
B) in a copper layer as a trace without connections: assign a unique net name & enforce all DRC rules
C) assume island is part of a fill: (i) refill-then delete the island (ii) highlight island as either warning/error and prompt user to correct
Thank you all,
The boardhouse replied:
“The spacing between the via hole and BGA pad is OK for us.”
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