Clearance rules

Layout
1

Is there a trick for those via clearance settings? I have a design rule set to 0.5mm for hole to hole:

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In the netclass however, I set the net clearance to 0.25mm, with the via annular ring of 0.15mm this results in a hole to hole clearance of 0.4mm.

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My issue now is that when routing these 0.4mm are used when placing tracks as the minimum clearance where it snaps against. However, the global minimum distance is 0.5mm which causes all those DRC errors.

Is there a way to fix this without me increasing the netclass distance which would also change the distance between traces? I also don’t want to manually make sure that the distance is the required 0.5mm.

Thank you!

Application: KiCad x64 on x64

Version: 9.0.1, release build

Libraries:
	wxWidgets 3.2.6
	FreeType 2.13.3
	HarfBuzz 10.2.0
	FontConfig 2.15.0
	libcurl/8.11.1-DEV Schannel zlib/1.3.1

Platform: Windows 11 (build 22631), 64-bit edition, 64 bit, Little endian, wxMSW
OpenGL: NVIDIA Corporation, NVIDIA GeForce RTX 3060/PCIe/SSE2, 4.6.0 NVIDIA 572.60

Build Info:
	Date: Mar 30 2025 01:11:30
	wxWidgets: 3.2.6 (wchar_t,wx containers)
	Boost: 1.86.0
	OCC: 7.8.1
	Curl: 8.11.1-DEV
	ngspice: 44
	Compiler: Visual C++ 1942 without C++ ABI
	KICAD_IPC_API=ON

Locale: 
	Lang: de_DE
	Enc: UTF-8
	Num: 1.234,5
	Encoded кΩ丈: D0BACEA9E4B888 (sys), D0BACEA9E4B888 (utf8)
2

I guess I could write a custom rule for this. However, this seems to me like a basic issue that shouldn’t need a custom rule

3

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This seems to be a KiCad 9 bug - in KiCad 8 this works as expected. I’ve used the same design rules and net classes in both projects

4

Created an issue: Hole-To-Hole Distance is overridden by netclass clearance (#20714) · Issues · KiCad / KiCad Source Code / kicad · GitLab

5

did you find a work-around yet?

6

Can you try with the nightly build please? I pushed a fix for an issue which sounds very simliar! (Will be in 9.0.2 when we release that soon).

7

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I’ve installed this version and it is still an issue with it: kicad-nightly-9.99.0.1132.g883a1f8d97-x86_64.exe

As you can see, the 0.15 mm copper clearance is respected:

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But not the 0.5 hole to hole clearance:

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8

my current workaround is to manually make sure that the clearance is right. Since the current project only has a few vias close-by this is doable for me