In my PCB layout I have about a dozen or so 2mm traces that require a clearance of 0.15 inch from the copper pour. I see you can set the copper pour clearance globally by double clicking on the copper pour area, then under Electrical Properties you can set the Clearance. This will apply to every net related to the copper pour.
What I wish to accomplish is actually the reverse situation. I wish to define a clearance for certain nets only. Any help or suggestions would be appreciated
Karin
KiCad always put a clearance around each and every net. No single net can come closer to any other net then it’s specified clearance. If it does, then this WILL generate a DRC violation. Clearances may overlap each other, but a clerance may never overlap with copper from another net.
Normally this is handled by net classes. Net classes are a very important concept. Read in the manual on how to use them effectively.