When trying to route my reference voltage traces to an output pin of an isoamplifier, the clearance for the trace from the filtering capacitor to the pin (#6) does not seem to autopopulate after a re-pour. You can also see that I’m having the same issue with the power input (pin #8). I believe that this is because that kicad would like to connect pin 6 and 8 directly to the 5V power plane, however, I would like to run the signal through filtering capacitors first. I’ve manually overridden the connection to copper zones on pins 6 and 8 so that there is no connection to the plane. However, when connecting the capacitor to the iso-amp pins, the trace is just laid down on the power plane with no clearance, which I assume will just completely bypass my filtering capacitor.
I also get a DRC error: missing connection between items, Kicad seems to think that the 5V track going into TP7 isn’t connected to the 5V zone? I’m not sure what’s going on here either.
When I try changing the net labels on the schematic, they are just overridden by the 5V power net label during ERC. Changing VREF to a different power port does not seem to work as this completely disconnects it from the 5V power plane.
Is there any way to force clearance? Have I completed my schematic incorrectly? Any tips are appreciated. See the pictures attached.
I think there may be 2 ways to get to where you want to be . . .
You can create a keep out zone so the pour does not make the connection between pin 8 and C11, that will just leave your track to make the connection.
Or . . . you could have the connection between pin 8 and C11 on a different net and not on the +5V net, the pour will clear the pad (8) and track to C11
This solution is almost perfect. Thank you! See progress pictures attached. I had to override the copper zone connection to no connection on the 5V side of the net tie. You can also see the clearance around the 5V pad is larger than others, possibly because of my default power plane settings which I need to look into. I wasn’t able to override this on a per pad basis. Another annoying thing is that I was thrown an ERC error to pin 8 as it is not seen as driven anymore by kicad, the current solution is to put a power flag on it but it certainly clutters the schematic a little. In the DRC, I also get an overlapped courtyards error which I assume will not be a problem.
I have one last problem though, the DRC still seems to think that there is a missing connection between the net tie pad and the copper zone, as evidenced by the rats nest going off screen and ending at the edge of the 5V plane. This is the same issue I mentioned in my first post. We can see that the pad is connected to the 5V plane through pad one of C15. So if I can’t figure it out, I think I can ignore this? But it is nice to get rid of all DRC errors. I’m using kicad v6 if its a possible bug.
For future forum readers:
I had not heard of net ties before today. Here is a fantastic Phil’s lab video about them:
I’m using kicad v6 so there were no footprints in my library. Here is a footprint library for net ties for those that don’t have it. Though, I had to modify the SMD net tie to fit my 0.3mm tracks.
I have one last problem though, the DRC still seems to think that there is a missing connection between the net tie pad and the copper zone, as evidenced by the rats nest going off screen and ending at the edge of the 5V plane.
There should normally no ratsnest left at the end - this is one of the DRC-errors one should take serious.
You have to upload your zipped archived project (kicad main manager–>File–>archive project), so we can look at the board and try to find the cause for that remaining ratsnest-line.
guess: you have some non-connected zone-fill-islands which are separated by tracks.
