Clearance for vias

Hi,

where can I set the clearance for vias? Track width/clearance is set to 0.11/0.19mm, that works fine. I use two inner power layers and the clearance for vias there is 0.5mm.

How/where can I reduce that to 0.2mm?

Thank you
Cheers
Detlef

There is no separate clearance for vias. Clearance for via’s is the same as for tracks and pads, and they are set with Pcbnew / File / Board Setup / Design Rules / Net Classes

Normally clearance is inherited from the net class that a pad, track or via belongs to. Pads of Footprints have some special rules. They can override the clearance if told to do so explicitly, and you can do that by editing the properties of individual pads. (Or use the Footprint editor for more editing comfort).

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Hm. Width/Clearance for NRST_SCO is (default netclass) 0.11mm/0.19mm . On the inner powerlayer the clearance shows up with 0.5mm. Thus I loose too much copper.

Where is my misunderstanding?

THX
Cheers
Detlef

What is the clearance for the netclass of the net of the power plane? If it’s 0.5mm the large clearance comes from that.

If you want to keep it that way in outer layers, what you want isn’t possible in KiCad version 5.1. The clearance comes from the two netclasses (the net of the via and the net of the power plane) for all layers.

Only in 5.99, the unstable development version leading to v6, it is possible to define detailed rules which would make this possible.

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Ah, clearance has to do with TWO nets! I understand, thank you very much, I set the clearance of the GND and 3V3 nets to 0.2mm.

THX
Cheers
Detlef

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Indeed. Each net has it’s own clearance, and clearances may overlap, but a clearance may not overlap copper of another net.

It may also be more clear if you turn on the displaying of clearances for the tracks themself: Pcbnew / Preferences / Preferences / Pcbnew / Display Options / Clearance Outlines / Track Clearance / (*) Show Always (Or whatever other setting works best for you).

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