Chips with distinct pin numbers per footprint type

Some chips, like SST39FS040 (http://ww1.microchip.com/downloads/en/DeviceDoc/25022B.pdf) have distinct pin numbers associated to a specific function, depending on the footprint of the chip.

For example, the SST39FS040, defines the Data pins has:

  • PDIP footprint:
    DQ0…DQ7 = 13,14,15,17,18,19,20,21

-TSOP footprint
DQ0…DQ7 = 21,22,23,25,26,27,28,29

Which are clearly different.

Since matching the footprint with the schematic part library is done using pin numbers, and not pin names, we need to be able to have different pin numbers depending on footprint type!

But I believe this is not possible. or is it ?

I don’t see any other solution, then to duplicate the part in the library with a different name, like “SST39FS040-TSOP” and correct the pin assignments.

NOTE: I had a library “memory” with a part named “SST39FS040”, which has the PDIP pin numbers.

IMPORTANT: Due to this, I almost sent a PCB to manufacture, before realizing that pins where incorrect for TSOP version.

The major problem, is that this kind of error is silent.
We will only find the problem, if we start checking pin by pin.
Which in turn makes us not trust parts in libraries.

Clearly this is nothing new, and there should be a way to assign pin numbers depending on footprint type, but apparently it’s not possible.

That’s the way to go.
And that’s why most of the more seasoned users of KiCAD work with Parts instead of Symbols+Footprints. :nerd:

Apparently there is a footprint filter, in the part properties dialog, which might help to avoid selecting a non compliant footprint.

I wouldn’t know… I use my own libraries that have all the information in the part name to get this sorted.

This is a ageless and universal problem - both old (look at TQFP44 / PLCC44 / DIP40 MCUs for example)
and new, where modern tiny BGA CSP footprints will use BGA conventions.

Yes, you do need to check package carefully, and a part name that includes the package-pinout, is a good idea.

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It would be a lot better, if a part could have a generic name, and then it could have pin mappings depending on packaging type.
This would minimize clutter in library lists, and would prevent errors, since it could match the packaging type with the footprint type, to see it they were the same/compatible.

Maybe an idea for future developments.

As a side note, libraries, should be able to associate parts with TAGs, so that the same part could be listed in more than one category.

Example: “Memory” and “Microchip”.

This would also come in handy, when one manufacturer buys another, we would just need to add a tag to the existing parts. :smiley:

Having a single “category”, seems a lot like directory listings, where a file typically is only in one specific dir. This is so 20th Century.

If you wanted pin-numbers to smart-change based on footprint that would require a live backward link from PCB back to SCH, so when a change in footprint was done, the SCH pins are updated.
Plus, you need to pass that information into the BOM side of things too.

It also means the Libaries have become more complex, not simpler, as you need to create multiple correlated mappings at the create time (and this imposed on a designer already being asked ‘is it done yet’ by his boss).

All up, it looks to cost more time, and have more risks, from the “I’ll finish that later” syndrome.
The problem it ‘solves’ is also not much of a real issue - it is quite rare the change packages, in the middle of a design.

Given BOMs are driven by a known part order code, that is the way most designs are done.
ie ONE piece of information to manage, not many.

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It would be better if the incompatible parts had totally different part numbers. Saves a lot of purchasing errors. RS and others do this with their numbering

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If you wanted pin-numbers to smart-change based on footprint that would require a live backward link from PCB back to SCH, so when a change in footprint was done, the SCH pins are updated.
Plus, you need to pass that information into the BOM side of things too.

I believe you miss understood what I suggested.

What everyone is suggesting, or using, including me, is “create another part with some reference to the footprint in the name”.
This works, with what we have now.

What I was suggesting for the future, is that a part could have a property/list of applicable “footprint types”, like PDIP, SOIC, SOT, etc…

If this property is not defined, it’s the same problem as today, so backwards compatible.
If the property is defined, it means the pin numbers are only valid for those specific “fooprint types”.

And I would like to stand out the TYPE in “Footprint type”, which is different from just “footprint”, since it doesn’t defined any specific physical pin layout. It just confines the current pin numbers to ve valid only on these types of packaging (footprint).

This is better than just create another part), because you could have different pin numbers, on the same part, you just have to choose the correct mapping. Similar to what you can already do today, by selecting the part “footprint” in schematic editor.

So there is no need for complex feedback loops on information, is just a property, like for example “color”, the distinction, is that it would provide distinct pin numbers (a mapping) to schematic part.

What I’m talking about is data structure and how to use it.
I’m a software engineer, so I would like to think that I know what I’m talking about :slight_smile:

I understand that the system has a very tight definition of pins with numbers, but it should be possible to change pins definition, to get their pin number, from a specific mapping, and eventually even have one mapping as default (DIP or PDIP ?).

Hope this clears up my suggestion.

This is not the problem I’m trying to solve with my suggestion.

The problem is that we add a part in schematic, without thinking of “footprint”, in this phase, which is logical and why the schematic/fooprint separation exists (keep this info separated).

However, we should be warned, if the part we are using has some specific peculiarity, like for example, when we use a device with several gates or instances of the logical device.

Basically a device with several “fooprint” mappings, has several instances, and we need to choose one, to prevent pins changing later, if we postpone the “which package ?” decision.

Well, KiCad doesn’t have a notion of a “part” as a separate entity that maps symbol pin names to footprint pin numbers (this mapping is currently done in symbol itself). Perhaps in the future it will change.

As I software engineer, I also used to think that the logical separation was useful, but after a while I realized that reality does not match the logical model! Manufacturers create the same “part” but with quite different pin outs. The footprint is definitely not a trivial property like “color”, it changes fundamental stuff. KiCad would have to be a lot more complicated to capture all the nuances.

Given the KISS principle, I now veer towards one unique part per footprint. I’ve been bitten a couple of times by bad footprints (incorrectly mapped to footprint),. so I think less rope is better than more rope.

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Funny enough that is EXACTLY what I’m suggesting, the problem seems to be that I’m not the correct lingo :slight_smile:

I was calling a part, what you guys call a symbol,
Apparently Kicad calls it a “component”, so I’ll call it that.

So a “component” should have a way to relate to it’s physical properties, pin numbers/footprints.

The separation between logical and physical properties is useful, because it allows to re-used these definitions. We just need a “flawless” way to bind them together.

NOTE: I’ am also an Digital Hardware engineer, and I have also been bitten by the wrong part being bought, but fortunately, always with very small batches.

Nice and useful description Andy_P
And that idea of a local Master Library, should be endorsed by each E-CAD package in existence.

Independently on how every one works, each as their own work flow peculiarities, we all have the same goal: to never fall into the trap of ordering or using the wrong part (A.K.A component).

However, I believe the problem is in application work flow, how it was designed and why.

Current work flow, is something like this ( in a very reduced form):
1 - Create schematic, using components (AKA Symbols), NOTE: components have pin numbers.
2 - Associate Footprints to components (implicitly matches pin numbers with foot print pins )
3 - Create PCB using the above.

The problem, as I see it, is in point 1 and 2.

Point 1: From a logical (schematic) perspective , we shouldn’t care what the pin number is, but what its’ function is in the device (example, 74xxx family with several gates per package).
Granted that having pin numbers is nice to review or debug the PCB later.

However, from a logical perspective we could do without them, and this would avoid some problems (I’ll explain more later).

Point 2: The big NO-NO in this step is the “(implicitly matches pin numbers with foot print pins )”.
Pin numbers, should never be implicit, either someone already did that mapping or it needs to be done.
The component should never assume anything, since this is what causes problems.

Once someone associates a component (symbol) to a specific package type, using “Pin Mapping”, then there is no doubt, that “component” is applicable to that package type, else it’s not, and we shouldn’t see pin numbers on the symbol.

It doesn’t matter what name you give the part, each one to his own liking.

What I’m saying, is that is that instead of 3 steps, we should have 4.
1 - Design Schematic using (AKA Symbols), NOTE: (with or without pin numbers)
2 - If not already done,Associate/Map component pins to Package Type. NOTE: Once done this is saved within the component definition.
3 - Associate Footprints to components/Pin Mappings (no implicit conversion here).
4 - Create PCB using the above.

Points 2 and 3, will be done only once for a specific device/package type pair.
And once done, you will never do it again (for that component/package pair).

This still maintains the logical and physical separation, so that we can re-use symbols or footprints, to define a new “real part” software representation, but still allow to correctly associate components/pin numbers/footprints, without any assumptions.

And better yet, it allows several possibilities of work flows, with just the logical symbol, or the symbol already associated with a package type, with some specific pin mapping.

The real problem is that pins, implicitly have pin numbers, and footprints associated those without any human verification, and that is where the problem is.

Resuming, current component libraries, associate a component logical pins with their physical numbers, but forgot to save to which package type they apply to, and that’s the origin of the problem.

Did you read what I wrote ?

That’s exactly one of the possibilities of what I proposed.

Yes, the problem is what underlying structure to use for binding.

Obviously, that’s why the software must be flexible and support all cases.

[quote=“Andy_P, post:20, topic:3584”]
For example, you seem to advocate that pin numbers aren’t important. But with FPGAs, pin numbers and pin assignments are VITALLY important. With all of the rules regarding banking and what pins can be part of differential pairs, what are power supply pins, and on and on, the pin number has to be on the schematic.[/quote]

No I don’t advocate that pin numbers are unimportant, I said:

From a logical (schematic) perspective , we shouldn’t care what the pin number is, but what its’ function is in the device

When we analyse a special case of a programmable device, obviously pin placement is important, because we can change the pin function/location !

That’s my current board case, where changing PLD logic output pin numbers is a tool to simplify board routing. I did go several times back to schematic, just to simplify my routing and optimize the board.

But that doesn’t go against what I said.
You can work with the component (symbol) without binding it to a specific pin mapping (assign pin numbers to pins), but you also can bind them and use the bound component, when that is the case. Ypu choose which, software doesn’t force anything on you. It’s the best of both worlds.

What we need to avoid, is software “assuming” stuff, that might not be true.

I believe we agree on what we both are saying, but I think you are mainly focusing on how to use the software, and I’m focusing on how to improve the software, to be more flexible.

Same goals, just different perspectives.

Cheers.

Yup, and is it that Data Structure I was addressing.
Mentor gets close to what you imagine, but even they fall short because they lack the new links your new data structure demands. Those new links make parts harder to check, and BOM extraction more difficult than it is already.

Yet those links are unused in 99% of all designs, which do not mix footprints.

Mentor have alternate decals for SCH and PCB, which permitted a casual change at either end, but this has fallen into less use, because of the weak BOM management.

There are good reasons part-ordering-centric design is used more these days.

Adding steps does not simplify things.
What you describe is close to how Mentor can manage things (they have a 3 piece data-base), but even they lack a means to cross-lock the package at both ends.

If you allow Multiple package choices at each end (as they do now) the weakness is someone can place a PLCC footprint, and draw a TQFP one, and it all looks valid.

So you must add a new structure that locks PLCC in SCH to PLCC in PCB, and once you have that, you have turned your nicely free & late footprint choice, but complex, library, back into a PLCC specific one.

Your Data base also requires that someone create all footprints when they make the part - but they already KNOW they will use only one - so what will actually happen ?
Of course, they will make only the one they need.

You need to sell this idea to the Part Vendors, as they have more time & motivation to create all packages.

A PCB designer does not have that time to spare.

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You are judging my suggestion, with knowledge tinted with how others have implemented something similar but different.

I never mentioned links.
Links is bad, because it blurs the ownership of the data.
Some data must be owned by SCH, some must be owned by PCB, and they should never be mixed. Even netlist, which is a shared resource, must be owned only by SCH.

At the most what I suggest is the exact same as filling in a component with everything you need in the current scheme of things, it’s equivalent, just more flexible.

What you refer to as part-ordering-centric design.

NO, it does not.

My suggestion just provides a way to guarantee, that once you assign pin numbers to a component, a “package type” will be guaranteed to be associated with it. It might not have a footprint yet, but if it has pin numbers, then it must have a “package type” (DIP, SOIC, TSOP, BGA, etc… it should include the pin count, like SOIC-32, for example).

As I said before, and this is the key issue here:

Resuming, current component libraries, associate a component logical pins with their physical numbers, but forgot to save to which package type they apply to, and that’s the origin of the problem.

Pin Numbers without an associated package type, is a big NO-NO.

P.S.
This is starting to get a very lengthy discussion from a simple suggestion. which can be good in a way, in that I seem to have stirred the pot :sunglasses:

No, I am thinking ahead to how this must actually be implemented - you may have overlooked the links, but just " filling in a component " is not enough - you have to ensure that with all this flexible M Symbols <-> N Footprints, that only one valid combination is possible. Anything less, is more dangerous.

Remember, PCB and SCH are separate executables, and communicate via netlists.

That one is really easy to solve, just use the footprint in the save-name. Already common.