Hello All,
Has anyone tried using KiCad to do Interposer designs for Chiplets? I’ve been playing with wire bonding lead-frames to die using a script to take DEF and create a footprint and symbol for the die and the packing wizard for the lead-frame. I would expect an interposer wouldn’t be a stretch since it is technically the PCB and the chiplets are the IC. I would say the only limitation I’ve run into is the scaling since chiplet bump pitches are in um vs mm, and the packing wizard should have an option to generate a generic symbol for the footprint it just made.
I do not know what are interposers and chiplets and maybe others on the forum do not either. Maybe include a few links in your next post?
Never done one, but if the job is done with ‘standard’ PCB and DevTools, probably KiCad can do it (or be modified to)
the minimum grid spacing currently doable is 0.001mm:
KiCad’s native resolution is in nano meters, so there is plenty of resolution.
I tried to set a small grid in the preferences, but KiCad complains and the smallest it will accept is 1um just as Claudio.Lorini mentioned.
You will also bump into other limitations / bugs at this scale level. For example: PCB Editor / Inspect / Measure Tool is struggling with this resolution.
I’m not a KiCad developer, but I guess that support for fine pitch stuff will improve over time, but at the moment the KiCad development team is still quite small, and there are many feature requests, and features that appeal to a small set of the users have a lower priority.
You can create a test project to find out how good it works for you and get an overview of the most pressing issues. If you’re really serious about this, then contacting https://www.kipro-pcb.com/ is an option. They do commercial support for KiCad (so it’s not free) and they also do priority development and bug fixes for customers.
I’m in the investigation side of this. So far, wire bonding QFN packages KiCad is a go. Just need to dig in more and I will update as I learn more.
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Never done it myself, but did see some youtube video’s about wire bonding. All the magic needed to make wire bonding work, is build into the wire bonding machine. In the video I remember, first chiplets were glued on the PCB roughly inside the wirebonding location. Then a camera in the wirebonding machine takes a picture and analyzes both the PCB pad coordinates and the exact orientation of the chiplet, and then makes all the wire bonds automatically. (Something like 50 wires in 3 seconds) I don’t see any problem for designing footprints in KiCad that can be used with wire bonding techniques, but there are probably specific requirements for the materials of the PCB itself, but that’s part of the ordering process.
Seems like what you need is a “scaler” utility. Setup your design rules and footprints at a larger resolution and create your design, then scale down the Gerbers (or whatever your output format is) to the needed resolution.
That could work. Some people used to scale things in eagle to get around the board size limits of that program. However, KiCad already uses nanometer resolution internally, and has plenty of resolution. I would much rather see bug fix requests to make direct use of that resolution.
It would be nice to have a scaler utility just because the page text box is bigger that the interposer and all detail is lost when viewing the page. It’s minor really since you can zoom in, more for pdf documentation.
I spent some time seeing what other tools do and the KiCad updates seem minor given all the other things are now in place. 1um grid spacing it about the right resolution for flip chip and wire bonding placement. The description Paul gave is basically correct. There are 3 materials used for interposers, ceramic ($$$) and organics ($ basically very thin PCB with much smaller features size capabilities, and PCBs know as chip on board (COB). The organic interposer and COB both use all the native settings in KiCad: PCB stack up, trace width and spacing, and blind vias, however there are no through hole vias for an interposer. What KiCad needs is an additional set of connection layers (die pad and wire bond), die pad has addition info for its height from the interposer surface, wire bond layer (it will require a wire diameter, material, and bend profile for calculating die to interposer impedance), and last a weld points (basically a via without a hole) to make netlist connections. Since the bonding wire has a profile, it is possible to place passives like R & C between the die and bond point given the component height doesn’t interfere (likely a bad idea for the scope of the initial feature). Seems simple enough…
I talked to Seth and Wayne at KiCon too, so it might be a pay for feature if the price is right 
Needless to say, I’m working on a requirements doc. So open to input before I get too far. Worst comes to worst, I might roll up my sleeves and put my SW hat on for a week or 2, assuming I can get up to speed on the build and validation environment.
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This is always a possibility with oss, but having heard the numbers on lines of code of KC, i suspect that dipping your feet in the inner architecture of the SW will take you much more than that…
Please, if you arrive at some solution, keep us here informed, I’ve never had the need for this feature, but in my line of work who never knows.
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I love to see KiCad extending into other areas such as this. A feature request for custom scaling factor seems like low hanging fruit. Designing an 15x15mm interposer on an A5 sheet does not make much sense, but you can set a custom paper size (with a scaled down title block), and then “print to size”. For very large PCB a scaling factor also makes sense. A simple solution could be to just define very small and very big paper sizes, and then only scale the title block.
I just attempted to add a grid that is smaller then 1um, and KiCad V8 rejects it:
If KiCad V9 still behaves the same this is worth a bug report / feature request IMHO.
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I got the same error too in 9.02. It will do 1um but not 100nm.
That’s enough to start creating a feature request. I won’t make it myself because I’m still on V8.0.9. Are you familiar with gitlab? Do you have an account there? If you make a feature request, then also add cross links to this forum thread, so people who want to follow the whole story can easily see both sites.