I have SMD power mosfet footprints from V5 and V6 projects that use an 8 pin package with a power pad.
1, 2 & 3 (source) are drawn connected on the schematic, 4 is gate and 5,6, 7 &8 and also the power pad are drain. Again my symbol draws these as externally connected pins.
Now on V6.99 I get warnings about overlapping pads, this is changed behaviour. Any suggestions how to fix this?
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I use one small pad for the gate, one larger rectangular pad for the source, and one largest rectangle for the drain. I guess this does not answer your question, but it works well for hand soldering. I am referring to MOSFET packages such as Infineon PG-TDSON-8 (roughly 5 x 6 mm) or PG-TSDSON-8 (That one is roughly 3 x 3 mm).
Be careful! These Infineon package designations are confusing as heck.
I have boards in production using my footprint, with good yield
I like to follow the manufacturers pin numbering strictly.
This footprint inevitably shorts pads.
Older KiCad versions suppressed the error when the pads were connected on the schematic
Because you have the pads with different numbers (5/6/7/8) instead of all the same number, you need to mark this as a net tie in order to not get warnings (technically you could connect these to different nets in the schematic)
In 6.99 you can specify which pads are the net tie in the footprint, and it doesnât disable all checks. Because we added this flexibility, we also added more checks that pins are not allowed to overlap unless they are specified as net tie pins.
Trying the net-tie method, I cannot clear the error
I notice that the symbol and footprint libraries for this package work around by merging 5-8 into one pad 5
It was a good test-case. The main error is that we were using FindNumberedPad() in the net-tie logic, but it only returns the first pad of the given number.
But there were two other unrelated bugs that it turned up, having to do with how we check netties in zone filling and the router.