Capacitor (0402) smallest footprint

In Kemet’s datasheets (e.g., https://api.kemet.com/component-edge/download/datasheet/C0201C820K3GACTU.pdf) they show land pattern design recommendations as per IPC-7351.

For density level C (for high component density, thus the smallest land pattern), they state:

Before adapting the minimum land pattern variations the user should perform
qualification testing based on the conditions outlined in IPC-7351

Can someone comment on what they mean by this? What does “qualification testing” mean in this case?? And what are those conditions they’re talking about? Do I really need to read that IPC-7351 document? Is it a matter of just talking with the company that is going to do the assembly?

Don’t know that standard.
I suppose that if company that will be assembling the PCB accept your footprint than it is OK.
When I got KiCad for the first time (just 4.0.6 was changing to 4.0.7 I noticed that 0603 R footprint is made such way to make me to like it as I could go with two tracks 0,2mm under that resistor (never before I had 1mm space between 0603 pads).
I asked my contract manufacturer and they didn’t agreed for that footprint even it was directly taken form one datasheet - they used resistors from other manufacturer with little different pad dimensions and told me to have footprint designed to not only one manufacturer.
About testing - I don’t know but may be it is to check if elements placed on such footprint will not stand-up during reflow.

The version 4 footprints for passives were shitty. Don’t use them. Just don’t.

IPC-7351x (x=None, A or B) are THE industry standards for deriving footprints (or more precisely the land pattern) from the part dimensions, its tolerances and your manufacturing tolerances.

The equations given in these standards not only use the part dimensions but also a target solder fillet size. Every such standard gives 3 such fillet sizes for different “densities”. The highest density results in the smallest pads. It comes with the downside of not really fitting a part at the extreme edge of the tolerance ranges. The note you cite is about the highest density rating. So what they say is that you need to evaluate if you can live with the reduced yield that comes with using this fillet goal.

In other words they suggest the use of medium or low density settings as that will improve your yield. A further improvement is optimizing solder paste placement. The footprints in the official lib are scripted with medium density IPC-7351B settings and also paste optimization as per a paper that i don’t want to search now (It is 3 in the morning).

You can use the same script to generate footprints specialized to your parts dimensions (and i think you can define the density somehow but i don’t know how right now and well its still the same time so i don’t really care to look it up). Script is found here: https://github.com/pointhi/kicad-footprint-generator/tree/master/scripts/SMD_chip_package_rlc-etc

1 Like