I’m developing a board (4-layers) which has some capacitive probes - basically copper traces. These traces must be placed in inner layers.
First try: I drew the traces directly in Pcbnew but the net was not exported from Eeschema because it’s composed by a single wire only (and a label, but it makes no differences)
Second try: I tried to make a new footprint but the editor does not allow to select inner layers, only top or bottom.
Here I found a very ugly hack: draw the footprint in any layer and then edit the text file to assign copper to the desired layer.
It may work for a specific project, but it’s against all the rules to reuse the component!
How I can achieve the goal in a more elegant way?
Basically, either:
create a net even if there is only one wire (I cannot use a test-point because it requires a footprint…)
KiCad has some kind of limitiation of not wanting to put footprints on inner layers.
I just did a simple test though with first drawing Pcbnew / Place / Polygon, and then editing it’s properties withe e and I could move it to an internal copper layer without problem.
What is a problem is that KiCad does not want to connect a net to such a piece of copper, It wants a pad of a footprint to connect a net to.
To do this in KiCad is to use a THT pad, and then combine it with the graphics to make a custom pad. The Footprint Editor does not want to have anything to do with internal layers and that leaves hacking into the files to put the graphics on an internal layer.
It is a known problem, but I have no Idea when one of the developers of KiCad has time to pick this up.
There are also other valid reasons where footprints must be able to be placed on internal layers. For combined flex / ridgid PCB’s for example, not all layers exist over the whole surface of the PCB.
Do you know there is a wizard in the footprint editor for generating footprints for capacitive sensors? Footprint Editor / File / Create Footprint / 7. Touch Slider
(But it’s only on an external layer, so still the same problem).
I often use large areas of copper for a heatsink. I would like copper on all layers to help spread out the heat. It would be nice to have a foot print handle the inner layers.
In my “RF” work I often need a resistor with a shield layer right under it. I don’t have a good solution right now but I added two through hole pad that connect to pin-2 of the resistor and punch down through all layers. From the TH pads I connect to Layer-2 and then have to remember to add the shield by hand. It is nice to have SMD and Through Hole pads on the same part.
Now I realized that a TH part has copper on all layers. A SMD has copper on Top Only or Top+Bottom. (no inner layers) So what will happen if I make a topside SMD pad to solder to, then right on top of it make a 0mm hole with a large pad on all layers. Maybe I could make a pad on all layers to carry heat.
I don’t know how to solve the problem in post #1. I do have problems that are related.
The problem here is I cannot use a THT via/pad because the PCB will be submerged in water, so I cannot have anything (in the sensor area) on the external layers.
The suggestion to draw a copper zone on an inner layer is of course better then a polygon as I suggested earlier. You can give the Zone a net name, but the zone still won’t fill because it is not connected to a pad.
On gitlab, it was also suggested to make a custom shaped pad, but I still have not figured out how put such a pad on an internal layer.
Create a solid filled zone. You will need to ensure that there are no other tracks or components inside the filled zone.
Create a PCB-only footprint with a single “custom-shaped” pad. You will then be able to assign a net to the pad. Unfortunately editing the shape of the pad can only be done in the footprint editor.
There is also this request for a full padstack, which is somewhat related.
A work around might be to have a THT pad of that net (part of the footprint that is loaded from the schematic) in the part of the board that isn’t intended to be submerged, and run an internal trace to the zone. If the trace ends inside the area of the zone then it “should” fill. Granted, this is all manual chicanery…
Well, it works with the THT pad (i.e. testpoint) along the net. I don’t like at all this solution, but so far it seems the only way the designers of Kicad have foreseen for capacitive probes, RF antennas, and other (so weird) stuff…
@Amit_Bahl
The problem here is not how to draw tracks or zones on an internal layer (that is easy), but how to put a footprint with pads on an internal layer and to connect it to a net.
