Can I work Backwards in the Nightlies?

I have this LED board, and I’m trying to jam as many LEDs as I can on there for a test/experiment/whatever.

I’d like to take the PCBA and feed it back into the ESchema, but I don’t know if that’s possible with the nightlies.

Does anyone know if this “feature” (read “hack”) is possible?

It keeps surprising me how many people want to first make a PCB and then (sometimes) want to go backwards to get a schematic.

As far as I know there is no direct support for it and the main problem is of course that you have to place the schematic symbols on the schematic and add wires and KiCad needs guidance for that.

The simplest way for you is probably to:

  1. Draw one sub circuit in Eeschema.
  2. Use block copy to multiply it in ever larger blocks.
  3. Do the annotation in a logical way.
  4. Sync schematic with PCB.

But to sync annotation with the PCB you need either the “Timestamp” (UUID in KiCad V5.99) or the RefDes to be the same between schematic and PCB, and this is a problem at the moment.

There are two completely other methods.
One method is to use the “Replicate Layout” script (search this forum for it) A very short user manual:

  1. Draw a “hierarchical sheet” in Eeschema, which has one of the sub circuits.
  2. Insert that hierarchical sheet as many times as you need the sub circuit.
  3. Make a PCB layout for one of the sub circuits.
  4. Place one reference Footprint for each of the sub circuits on the PCB.
  5. Run the script, which will replicate the Footprints and PCB tracks to all the other sub circuits.

Another way is to use SKiDL.
SKiDL is mainly some helper libraries written in Python to generate schematic netlists and PCB’s from Python. With it you can use (nested) for loops to generate features such as schematic components, footprints and netlist connections and also make a PCB with it. There is an example project called “Studio Clock” for SKiDL.

With KiCad’s capabilities it’s impossible even theoretically. The layout file format doens’t have the information about symbols. The only way to connect symbols with footprints is to create a schematic, add symbols there and add footprint information to symbols.

It’s not possible to do that automatically from Pcbnew unless you write a python pluigin and implement some kind of footprint/symbol connection feature which would be somewhat similar to eeschema’s “CvPcb”. You would need to attach a symbol to each footprint. Then you should create a schematic and place symbols there in some arbitrary or logical order (like fooptrints are now added to a new layout when “Update PCB from Schematic” is used for the first time). Then you should either add net wires between pins automatically (extremely difficult, basically autorouting) or add a net label to each pin automatically, or do it manually.

As you can see it’s completely unrealistic. And if you want to do anything with that schematic it’s of no use because automatically created schematic would hardly be human readable or ready for further manual editing except for very simple cases. If you don’t need human readable/editable format SKiDL may be enough, it creates only netlists.

These are good reasons why such a feature won’t probably be implemented ever. I don’t believe any EDA package would have that kind of feature. It would be interesting to see if a python plugin could do that and to see if actually would be useful.

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thanks for this…i really dread using the python scripting, so i’ll try the hierarchical sheet.

Is there any offical documentation of the python API yet? I tried using it awhile ago thanks to one or two great tutorials online, but otherwise, i was greping through the package itself trying to figure out what did what…

Eeschema doesn’t have API yet, that’s in plans for 6.0 though. We also wait for a stable API instead of the current one in pcbnew which changes along with the C++ codebase. In any case it’s not well documented. Lack of manpower…

I would like to take back a bit what I said, “such a feature won’t probably be implemented ever”. There was some talk about it while the backannotation feature (Tools->Update Schematic from PCB) was developed, although it was deemed too complex and difficult to implement at that moment, and IIRC it was only about changing net affiliations. Something like that might work for small incremental changes provided that, for example,

  • a small change for an existing design is needed, where the schematic and pcb are already in sync
  • the change is made to the pcb, for example one footprint added and the pads added to nets
  • a symbol is linked to the footprint
  • the change is propagated to the schematic
  • in schematic the symbol is added like a footprint is now added to the pcb so that they are initially grouped, “floating” and must be moved and placed manually
  • the net labels would be automatically added to symbol pins
  • the user should manually draw the wires if the labels aren’t enough (to avoid implementing an autorouter which wouldn’t work well in any case – although an autorouter for schematic would be interesting indeed).

This would mean that pcbnew should behave like eeschema and vice versa. A more simple case would be to fix a logical connection error (nets of pads) in the pcb and propagate it back to the schematic. But in any case this would mean much complicated new functionality and much development work which would achieve little. After all, if you want to make changes to a design you have to make the changes manually somewhere anyway, and why not just make them in the schematic first as they should be done. Some simple things (refdes, value and footprint of an existing component, and net names) can now be changed in the pcb and backannotated to the schematic, which is good.

Thanks for this info…This is very helpful.

Would you happen to know when there’s going to be API for this?

Only that it will be before 6.0rc1 is released. The eeschema API issue is tracked here: