I’m tying all the 3.3V nets in my design down to a power plane via vias. Yet they’re still asking to be connected, even after being linked to the power plane.
Thoughts on what could be causing this, and how to fix it?
Causes already ruled out:
To be connected, a track must go to the center of the pad, it is not enough to be overlapping the pad (I don’t make the rules 
)
In this case, draw a thin track to connect pad 1 to the thick trace and it should go away.
Thanks. That did it for the one in the picture. Now going through to the (so many) other VDD33 connections that don’t think they’re connected and seeing if this same fix solves them.
Sometimes it’s easier or better to draw a zone. You just have to make sure that the combination of footprint’s, pad’s and zone’s pad/zone connection types is Solid.
I think the reason for the center connection requirement for pads and tracks comes from the easiness of implementation. If overlap would be enough, it would require checking minimum widths between crossings of outlines, or something like that, which could be codewise and computationally complex (I’m not sure, I don’t know geometric algorithms).
The endpoint of a track does not really need to be in the center of a pad. But it needs to fall within the area of the pad (or reference pad for complex shapes)
The “endpoint” is the point at the center of the arc. Not the outline of the arc. (With arc i mean the round end of the trace)
In this case the endpoint is far outside the pad area. (this is because the track width is extremely large for this small pad.)
However the performance of pcb_new increases if you place the endpoint at the center (At least this was the result reported on the mailing list a while back. It is only noticable if you have a very complex board with a lot of non centered traces.)
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