Buses and Hierarchical Sheets

[FS-RGE]

Thank you all for confirming that it’s not just me - and for the link to the GitLab bug.

Seeing the other forum thread linked:

Help: Strange ERC sub-sheet bus behavior

I’m trying to split buses, and I was getting ERC errors. So I made a test schematic to understand the behavior. I’ve attached pictures and the files. I think the ERC might have a bug. I’m using KiCad 6.0.8. On the left, I have an IC with 16 outputs that I make into a bus. I also have two instances of a sub-sheet that takes a 4 bit bus as input. I split the bus two different ways to connect the 16 bit bus to the 4 bit buses and they both work, albeit with some ERC warnings (“Both and are attac…

I can add that I tried the ‘unfold from bus’ ruse as well, and had similar results to those described there.

I hope this gets fixed soon; I like ERC, since it tells me when I’ve forgotten to do things. However, with 200+ ‘noise’ items it’s rather useless. My actual board has 8-wire buses, and I don’t want to have to split those up.

Despite this, I’m still a bit unclear on what’s supposed to be happening. With single wires, you can change the name as you go through a hierarchical pin. Nothing is ambiguous since there’s just one wire. But what about a bus? On one sheet those wires might naturally be labelled RESULT[0..7] but they would be connected to something wanting A[0..7]. How does that get resolved?