I’m trying to create a schematic where there are several ‘functional units’ connecting to a common backplane. I’m creating the functional units as hierarchical sheets, and creating the backplane on the top sheet as a few buses. However, when I try connecting things up, the Electrical Rules Check throws a tantrum. I suspect that I’m not quite understanding something about how buses connect through hierarchical pins (and how nets are named through them), but neither the manual nor the similar posts I’ve found have enlightened me.
When I run the Electrical Rules Checker, I end up with 24 errors (8 on each of the three sheets), complaining “Label not connected to anything.” It appears that each label gets this error on each sheet.
Even more strangely, if I go to lay out the PCB, the rats nest appears to have all the correct connections:
In 6.0.8 I did not experience this bug but definitely in 6.0.9 (most of my designs
have a hierarchical setup). 2 of my designs were checked with 6.0.9. and were
1 finished design was checked and improved with 6.0.8 (coming from 5.99).
But after the improvements with 6.0.8. I tried to check it with 6.0.9. to see if there
are more improvements (there were some indeed) but then this bug came up.
AFAIK the 2 pcb designs were not affected by 6.0.9 (if you ignore the DRC in the
This bug is already reported as issue 12814 BTW : it not only applies to buses
but for single nets as well. For this reason I reverted back to 6.0.8.
Thank you all for confirming that it’s not just me - and for the link to the GitLab bug.
Seeing the other forum thread linked:
I can add that I tried the ‘unfold from bus’ ruse as well, and had similar results to those described there.
I hope this gets fixed soon; I like ERC, since it tells me when I’ve forgotten to do things. However, with 200+ ‘noise’ items it’s rather useless. My actual board has 8-wire buses, and I don’t want to have to split those up.
Despite this, I’m still a bit unclear on what’s supposed to be happening. With single wires, you can change the name as you go through a hierarchical pin. Nothing is ambiguous since there’s just one wire. But what about a bus? On one sheet those wires might naturally be labelled RESULT[0..7] but they would be connected to something wanting A[0..7]. How does that get resolved?