Buses and Hierarchical Sheets

[FS-RGE]

I’m trying to create a schematic where there are several ‘functional units’ connecting to a common backplane. I’m creating the functional units as hierarchical sheets, and creating the backplane on the top sheet as a few buses. However, when I try connecting things up, the Electrical Rules Check throws a tantrum. I suspect that I’m not quite understanding something about how buses connect through hierarchical pins (and how nets are named through them), but neither the manual nor the similar posts I’ve found have enlightened me.

In simplified form, my schematic is:

Inside each unit, I have the following circuit:

(on the real board, the contents are different).

When I run the Electrical Rules Checker, I end up with 24 errors (8 on each of the three sheets), complaining “Label not connected to anything.” It appears that each label gets this error on each sheet.

Even more strangely, if I go to lay out the PCB, the rats nest appears to have all the correct connections:

As I said, I suspect there’s something I’m not quite understanding about how the bus wires get connected through the hierarchical pins, but nothing I’ve found has helped me understand what’s going on.

I’m using KiCad 6.0.9-0 on OSX 12.6.1 (Monterey/x64)

[paulvdh]

I have re-created your test project:

And with pretty much the same result.
I added names to the buses themselves, as I thought that may be the problem, but it does not help (much?).

I get “only” 16 ERC Violations of the type "Error: Label not connected to anything"

Here is the project if you want to see for yourself:
2022-11-13_asdf_bus_vector.zip (16.2 KB)

A few months ago I made a more complicated test project for buses, and I think it was bug-free back then, but now it throws 25 "“Error: Label not connected to anything” violations.

2022-07-09_asdf_hierarchical.zip (26.3 KB)

My best guess is it’s a bug in KiCad, introduced after July, but I do not have enough experience with buses in KiCad to be sure.

Just 3 weeks ago there was another user here with a very similar situation:

Help: Strange ERC sub-sheet bus behavior

I’m trying to split buses, and I was getting ERC errors. So I made a test schematic to understand the behavior. I’ve attached pictures and the files. I think the ERC might have a bug. I’m using KiCad 6.0.8. On the left, I have an IC with 16 outputs that I make into a bus. I also have two instances of a sub-sheet that takes a 4 bit bus as input. I split the bus two different ways to connect the 16 bit bus to the 4 bit buses and they both work, albeit with some ERC warnings (“Both and are attac…

[pedro]

As the netlists/ratsnest is right, I guess the error is in the ERC checker and not in the circuit.

I would try to lay some tracks and see if everything goes as expected.

[amtd]

Hi,

In 6.0.8 I did not experience this bug but definitely in 6.0.9 (most of my designs
have a hierarchical setup). 2 of my designs were checked with 6.0.9. and were
affected.
1 finished design was checked and improved with 6.0.8 (coming from 5.99).
But after the improvements with 6.0.8. I tried to check it with 6.0.9. to see if there
are more improvements (there were some indeed) but then this bug came up.

AFAIK the 2 pcb designs were not affected by 6.0.9 (if you ignore the DRC in the
schematic).

This bug is already reported as issue 12814 BTW : it not only applies to buses
but for single nets as well. For this reason I reverted back to 6.0.8.

Hopes this helps,

Armand

[FS-RGE]

Thank you all for confirming that it’s not just me - and for the link to the GitLab bug.

Seeing the other forum thread linked:

Help: Strange ERC sub-sheet bus behavior

I’m trying to split buses, and I was getting ERC errors. So I made a test schematic to understand the behavior. I’ve attached pictures and the files. I think the ERC might have a bug. I’m using KiCad 6.0.8. On the left, I have an IC with 16 outputs that I make into a bus. I also have two instances of a sub-sheet that takes a 4 bit bus as input. I split the bus two different ways to connect the 16 bit bus to the 4 bit buses and they both work, albeit with some ERC warnings (“Both and are attac…

I can add that I tried the ‘unfold from bus’ ruse as well, and had similar results to those described there.

I hope this gets fixed soon; I like ERC, since it tells me when I’ve forgotten to do things. However, with 200+ ‘noise’ items it’s rather useless. My actual board has 8-wire buses, and I don’t want to have to split those up.

Despite this, I’m still a bit unclear on what’s supposed to be happening. With single wires, you can change the name as you go through a hierarchical pin. Nothing is ambiguous since there’s just one wire. But what about a bus? On one sheet those wires might naturally be labelled RESULT[0..7] but they would be connected to something wanting A[0..7]. How does that get resolved?