I’m working on a board that contains a lot of hierarchical busses and, when I have tried to route this board, I have seen that some bus members are connected.
VFD contains D[0…7], ~{POWER}, ~{WR} and ~{RD}.
XMEM contains some signals (addresses and data), ALE, ~{WR} and ~{RD}.
When I route PCB, pins PG3 and PG0 of U9 are connected. Other connexion between PG1 and PG4. If I remember, ERC doesn’t return error or warning.
Thus my question is: how can I use two different busses that contain a signal with the same label ? For me, {XMEM} should contain XMEM.~{WR} net label, not ~{WR}.
Your'{XMEM}’ and {VFD} are just alias substitutions. If you want to use those alias lists in different buses, you also have to give the bus itself a name.
OK. But before posting, I have tried to replace {XMEM} by MEM{XMEM} (and all other busses). Of course, I have also replaced hierarchical pins and I only got a lot of errors… I will try again next morning.
First mistake is that you are using a lot of labels and buses, without first figuring out how it works. I guess that for every iteration, you change 20 or more labels. And because there are so many errors, it’s also easy to get confused.
Similarly, you have put a lot of netclass directive labels all over the place. Learn to use the other ways to put signals into a netclass.
From the screenshots I can not see how you defined your alias list. I only can see the members of the {VFD} alias list.
Next error, if you have named a bus, such as EC{VFD} then members of the bus get names like EC.D0 and EC.D1 You can also right click on such a named bus and then select a name from the Unfold from Bus sub menu.
Here a single defined alias with name abcd and members aa, bb, cc and dd.
