Bus issue between V5 and V6/7

[Uncle_Buzz]

Hi,
I did a board with V5.0.2 with buses and hierarchical sheets, maybe I used it in the wrong way but it did what I want in V5, but the same schematic on V6/7 is now doing a logical mistake… (maybe the mistake was the working V5 where it should not…)

To resume before some pictures : I have a repetitive sub-schematic part represented on a separate sheet, integrated multiple times with hierarchical sheets.

I have some bus A[0…7], B[0…7], C[0…7]
Each hierarchical sheet deals with half a bus (A[0…3] A[4…7] or B[0…7]…)
I divided each bus into two links (A[0…3] and A[4…7]), each link connected to a hierarchical pin on the hierarchical bus.
On the hierarchical sheet, I connected both half buses to the pins (1A0 = 1A4; 1A1 = 1A5…)
On V5, the schematic deals correctly with the connection depending on which half bus is connected through the hierarchical bus pin, but on V6/7 since A0 and A3 are connected on the hierarchical sheet, the connection is shared by both half buses…

Now some pictures because probably my words are not clear for unaware people of my goals :

V5 :
origin of buses with one channel highlighted (A0)

only half bus containing A0 is highlighted

hierarchical sheet linked to the half bus A[0…3] with A0 highlighted

hierarchical sheet linked to the half bus A[4…7] with no channel highlighted (A4 != A0)

V6/7:
not the same board since I didn’t want to edit the working V5, this an update of the V5 board with more buses, origin of buses with 2B0 highlighted (but only the channel is highlighted where the bus was although highlited in V5)

connection to hierarchical sheets (bus not highlighted)

hierarchical sheet linked to the half bus 2B[0…3] with 2B0 highlighted

hierarchical sheet linked to the half bus 2B[4…7] with BUS4 channel highlighted (2B0 = 2B4)

Is it possible to keep the same interpretation in V6/7 as in V5 or are we forced to link each channel on hierarchical sheets instead of half buses ? (the old way is way faster !)

[Tojan]

between v5 and v6 the rules for bus naming where changed in a way that renaming the bus on the way like you did does not work in any case anymore. I have some cases where it does and couldn’t figure out until now, what makes some work and others not. As far as I understood from other threads on this topic the idea is to use the Bus Definitionstool to manage aliases but I have not looked into that in detail until now.

[Uncle_Buzz]

I corrected my schema as below and it works (probably it should have been like this in V5 too):

the link between channels and bus is for reading purposes only, the correct naming is enough

Divide a bus as I did is no more possible since all the names put on the same graphical bus are aliases and not sub-buses like in V5, each sub-buses have to be drawn apart with the corresponding name.

To my mind, highlighting the channel’s owner bus was a better behavior in V5 because if buses pass through a hierarchical sheet, you can’t follow the highlighted channel if the channel is not drawn outside of the bus