Bus Hierarchy reports a LOT of ERC errors (KiCad 6)

[tobalt]

I attach below 3 screenshots of a small sample projects which illustrates my issue with the bus hierarchy. There is a main block (B) which contains two similar bus inputs “SER1” and “SER2”

These two busses connect via a top schematic to two instances of another block A:

Inside block A, I omit the full net names and use only the {bracket expression} for the 3 generic net names:

The idea is, that Block A1 connects to J3 in Block B and - likewise - Block A2 connects to J4 in Block B, with 6 unique net names.

This indeed works once exported to the PCB. However, I get a lot of ERC errors and warnings:

I interpret that ERC complains because the Netnames on the bus wires are different to the hierarchical labels.

But it is impossible for me to always use the full net name description in the hierarchical labels. The hierarchical blocks would look extremely big and ugly.

Can I safely ignore these errors/warnings or how should I handle this situation? ( I am very new to Kicad)

[cronJ]

Hi,

for your design, this works:

Root sheet:

A1 sheet:

B sheet:

The trick is to attach the bus signals on the sheet connectors. You can also use the bus alias feature, to generate an alias for many signals and place the alias into it.

E.g. if you have a bus called SPI{PICO POCI SCLK CS} you can generate a bus alias for SPI and rename the bus to SPI{SPI}.

[tobalt]

Thanks, I’ll try this. I wanted to avoid calling the hierachical ports with the full bus description…

It appears that the Bus Alias feature can at least help shorten these descriptions.

One thing I dislike about your solution is that to me the net names seem undefined, as they don’t appear unambiguously in the top schematic. In the top schematic there are two conflicting descriptions (one from A1 and one from B). So how is this resolved ? Or rather: will it always be resolved in the same way ?