Currently if I copy/duplicate a sheet that uses symbols declared in the root sheet, all the symbols within the copied/duplicated sheet will simply get assigned the first available units of the next symbol in the numerical order.
(in the image above I copied the SRLATCH-B-1-2 sheet, and it automatically assigned units A and B of NOR-3, instead of units C and D of NOR-2, which would leave 2 unused gates in NOR-2)
Is there a way for me to uniquely bulk assign the appropriate references and units of the 74HCT02 symbol across all the sheets within the hierarchy that use the 74HCT02 symbol, such that all available NOR gates are used?
Other than manually going through every sheet in the schematic hierarchy and manually assinging the appropriate references and units for every usage of the 74HCT02 symbol.
Thank you for reading my post, any guidance is appreciated.
As far as I know, there is no such automation in KiCad.
Pin & gate swapping is a long standing open issue (17 years!) on gitlab, and this is related. It’s one of the (ever smaller) gaps in KiCad’s functionality. Pin & gate swapping used to be a big thing 30 years ago, but PCB’s with many TTL IC’s are a thing off the past.
You may get some assistance, by assigning footprints and putting those on the PCB. That at least gives you an overview of unused gates.
Assuming I manually carry out the reference & unit assignments across all the symbols in my schematic hierarchy, is there some way of checking my work by visualizing any gates that I may not have used or used more than once on accident?
It is still a big thing - swapping bits and bytes within DDR busses, for example. Thing is, there’s a whole hierarchy of what can be swapped in such busses, and that (and other legacy issues) makes this really tricky to implement well. Definitely something we’d like to do - as ever it’s a question of finding somebody with the time to do so.
Yes, of course it’s still useful to have. One thing I have bumped into myself is routing microcontroller pins to (multiplexed) 7-segment displays or connectors. Pin order does not matter much. The method I use is to first draw an initial draft schematic, and when the routing on the PCB is problematic, I have both the schematic and PCB editors open at the same time and fix it manually. uC peripherals usually have a limited amount of pin configurations. That would add a whole database to the pin swapping, although for some uC families (STM32 notably) this database is already present in the “alternate pin configuration” for the symbols. STM32 looks quit complete here, I assume it’s scripted from the original design tools.
For FPGA’s it’s on a whole different level. Those can have arbitrary pin assignments, (with some timing constraints I think) For those, routing the PCB first, and then backporting the pin assignment to the FPGA tools (VHDL / Verilog) would be a nice option.
