I’m having issues where on a tight array of wide TO-92 footprints, trace clearances are not honored.
I’ve this on 3 different projects (2 from scratch specifically to test this with default library parts), tested on 7.0.5 and 7.0.6 as well as on a windows and linux machine.
Has anyone else been able to replicate this? Any good workarounds? (other than “carefully route”
thanks for your time
Bug? Trace routing ignores clearances - YouTube
Clearances can be set at a board level but also at a footprint level, this thread might help:
Parameters are distributed in several places and some of them are values ‘to be used’ and some are ‘limits not to be exceeded’.
I suppose that at Board Setup-Board Stackup-Solder Mask/Paste you will find 0.08 somewhere.
You are clearly trying to do it too fast. It is clear that you didn’t read the indicated by an arrow sentence.
Global settings can be overwritten by footprint settings and they can be overwritten by each pad settings. Zone fills have also their own settings. Net class…
Thanks for your reply!
The pads in question have “Clearance Overrides and Settings” set to 0.
Board configuration: Clearances set to 1mm, still have issues (as per
video, note how clearance rings indicate the required clearance, then as I move around, it tries to route around it, but in some cases ignores it?, it’s when it ignores it: that’s happening very often and is the issue).
Can you share the wole project?
Sure thing. Original project is proprietary, however I have created a new project to demonstrate.
I have simply placed two BC557 transistors, assigned them footprint: Package_TO_SOT_THT:TO-92_Wide
When playing around with routing, I can replicate the problem.
Zip file cannot be attached as I am new forum user. Please download using this onedrive link:
Microsoft OneDrive - Access files anywhere. Create docs with free Office Online.
You are now a “basic user” and should be able to attach. Please try.
your original video (and the track-stub to the left of Q2-pad3 of your example-project) shows a bug. The clearance in the video is most time respected, but sometimes inbeetween the track goes to close to the pad. I have seen this behaviour before (see issue
PNS-router: produces tracks with clearance error (#14659) · Issues · KiCad / KiCad Source Code / kicad · GitLab). After the fix the routing worked well for me (until now).
With your example project I can again reliable reproduce the clearance violation. For reproduction:
grid set to 1.0mm
it’s important to use only slow mouse-movements
start routing from Q2-pad2, move 2mm to the left (straight below Q2-pad3)
than slowly move mouse upwards - you will get a point where the clearance is violated.
If you want you could open a new gitlab issue. Add the video (embedded in the issue, not as youtube-link), the example project and a good description.
Seems to be OK upto and including 0.5mm but greater than that it goes wrong.
With smaller “Minimum clearance” it get’s harder to provoke the clearance-violation, but I was able to create one with “Minimum clearance”==0.4mm (needed playing with finer grid and careful mouse.movement). I think the bug is buried in the router-code, the minimum clearance parameter makes it only harder/easier to discover.
This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.