So, I am working my way through all things KiCad and I found an issue on my (VERYOLD) nightly.
In PcbNew I set the page layout from the default, to “USLetter 8.5x11in”.
The upper left corner was 0,0 , but the lower right corner was NOT “dx 11.0 , dy 8.5”…
I hit “F9” followed by “F11” and all went back to normal again.
I can NOT (yet) replicate this bug; although I was staring at it trying to figure out why this is happening.
AND, YES, I HAD SIMILAR ISSUE MORE FREQUENTLY WITH THE STABLE 4.0.5.
Which graphics mode were you in when you changed to US Letter the first time?
I had to actually go back and take a look…
The OpenGL (and Cairo) canvas shows the actual paper page outline; whereas the Legacy canvas does not.
I know this bug has been reported in the past, but this was with a completely blank new pcb layout.
I also don’t know if this bug has already been fixed in the nightlies; but this is extra info in case it has not been fixed.
The only problem with that is that only a handful of developers visit this forum regularly. You really should add your problem description to the bug report. (Maybe link the bug report here so that if someone on this forum finds additional information they can easily give this information to the developers.)
I do realize that this is just for discussion. I wasn’t ready yet to bother the developers, as they are aware of the problem.
But, I did find a “quirk” just now and I wonder if anyone knows if any of this matters.
This is what I got when I created a NEW PROJECT:
(edge_width 0.15) <—
(via_size 0.8)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524) <—
(pad_drill 0.762) <—
(pad_to_mask_clearance 0.2) <—
VS:
(edge_width 0.1) <—
(via_size 0.8)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.5 1.5) <—
(pad_drill 0.6) <—
(pad_to_mask_clearance 0) <—
That ^^^ is what I get after I DELETE the original created .pcb file (and the .bak), then have KiCad generate a new .pcb file; by launching PcbNew with the file removed from the folder. This is in setup line 46 - 63 in the .pcb file. So, somehow, there are TWO slightly different “setup creation methods” in KiCad.
It is a little bit unclear where to provide a bug report… got a link?
I interpreted this sentence by you as you have found a bug report.
Just in case you do not know about the bug tracker of kicad, here the link: https://bugs.launchpad.net/kicad
And here the official how to report a bug: https://kicad.org/help/report-a-bug/