Please explain. I have been using Power MOSFETs since they became generally available. I wish I still had the sample N channel Siliconix “VMOS” Power MOSFET which was blister packaged onto a piece of marketing cardboard. It was in a TO-3 metal case and was rated maybe 50 or 60 volts and had an ON resistance that I think was over 0.1 ohms. Not competent by today’s standards.
I do not understand the text outputs, but I see nothing wrong with the top of your three waveform plots. The drain is at 0 when the gate is at 12V and the drain is at 12 when the gate is at 0V. That is correct for a P channel MOSFET.
If the only difference between the top waveform plot and the other two is the value of the output load, then perhaps there is some source of leakage current in or around the MOSFET model.
The VDMOS intrinsic model parameters were not set to values found in typical transistors, e.g. they were Vt0=0, KP=1.
With ngspice-40 we will have default values similar (not equal!) to IRF540, IRF9540.
Just as you can’t pick a random FET from some electronics store and apply wishful thinking to make it work, you also have to know your spice models to be able to use them with any sort of accuracy. I don’t know what those Vt0=0, KP=1. numbers mean Holger mentioned, but for all I know, the built in PMOS may as well be some small FET with the size used on IC’s. All I can deduce from your graph is that it has an “off leakage” resistance of about 2.5k Ohm.
But a thumbs up for Holger, setting default parameters fit for a power MOSfet does seem more logical for simulating in KiCad.
Because it exhibits a reverse leakage current og 2.5 mA, which is unreasonable.
This makes me distrust the model completely. I’ll try rerunning the sim with a supplier model. Let’s see what happens.
So what?
There are plenty of logic ships that let out the smoke if you put more then about 3.5V on them, and each of the fet’s having a few mA of leakage will do that. But that does not mean the FET is faulty, it is just abused beyond it’s specks.
I have not looked into the specs of that “Vt0=0, KP=1.”, because that is completely irellevant in this context. You simply should never take some random model, make wild assumptions and then blame the model if your assumptions turn out to be false. It’s an inherently flawed way of thinking. Compare that with: “Hey, I have some weird results, I wonder what’s going on”, and then start diving deeper. At that moment it has become time to figure out what those parameters posted by Holger really mean.
Well, this started with an OP getting weird results on a simple buck circuit.
I have time on my hands at this point, so I tried to recreate it, using the symbols/models of the OP.
And I got weird results.
I started removing parts from the circuit to isolate the issue.
Next up was the PMOS model (the default VDMOS), and it’s non-functional.
So why is it included as PMOS model in KiCAD? Where did it come from? 6.0 didn’t have it.
I did a sim run using the IRF9540 model from Vishay (sifh9540.lib) and it’s spot-on:
I can agree that it’s an unfortunate combination of circumstances, but as I wrote before, I did manage to get the original “Buck” upload to simulate with minimal changes.
So for the sake of argument I did a fresh download of the zip file in the first post and:
Extract the project, and open the project and schematic.
Add a text line with “.tran 10n 2m” to the schematic for the simulation parameters.
Edit the inductor properties and change “Sim.Params” to “l=100u”
Edit the resistor properties and change “Sim.Params” to “r=10”.
Run the simulation.
Probe Gate, Drain and output.
With these minimal changes I get the following results:
And these results look quite plausible, so my conclusion is that the supplied “PMOS” does work, but it was just operated outside of it’s intended operating range. Both the model itself and the whole schematic are “functional”.
The “PMOS” does have a weird and extremely high leakage under these circumstances, but I do not dare to draw any conclusions from that. I simply do not have enough knowledge of ngSpice for that.
To your first point, I agree, it’s completely plausible for discontinuous operation, increasing load current would probably make it look nicer.
To the “PMOS” thing, I don’t know either. I’ll stick to using supplier models.
There is no reason for a typical Pch MOSFET to have leakage current above the microamp range. I just grabbed a Pch datasheet from my hard drive. IRLML9301TRPbF is a 30V Pch MOSFET in SOT23. It has an ON resistance of 64 or 103 milliohms depending upon the gate drive voltage. With 24V drain-source, the maximum drain-source leakage current is 1 uA at 25 degrees C or 150 uA at 125 degrees C. So using this as an arbitrary/reasonable benchmark, I think that the OP’s sim model is very leaky. But it does work.
In this context there is another inportant parameter in the IRLML9301 data sheet:
VGS(th) Gate Threshold Voltage -1.3 to -2.4 V.
Let’s say our device is typical and has a threshold voltage of -1.85V, which is negativ because we have a PMOS.
For gate to source voltages < -1.85 V (more negativ than -1.85) the transistor is on, for a voltage > -1.85 (towards 0) the transistor is off. This is the most simple model, in reality (and also simulated) there is a slight conduction (subthreshold or weak inversion conduction) even in the off region, closely to the threshold, decaying exponentially with VGS (the gate to source voltage).
The default model parameter for threshold voltage (Vth0, equal to VGS(th) from the data sheet) for VDMOS in ngspice has been set to 0 V. Why that? Because nobody did care about that, and people have been using vendor-provided models.
Now with KiCad 7 we have the selection of an intrinsic model, which exactly uses the ngspice default model parameters. Unfortunately nobody did test this combination, no reality check. So with Vth=0 and the subthreshold current simulated you may have a few mA of current with VGS=0 V applied.
ngspice-40 will have a modified parameter set, according to the PMOS IRF9540 data sheet the threshold voltage of this device will be around -3 V, and the leakage at VGS=0V is just the reverse diode leakage.
Thanks, holger. You have presented good stuff. Yes having Vgs (th) = 0V sounds like a problem. and a bad model. Coincidentally I am doing a lot of sims (more than I want) in my job these days. And while I have done simulation for many years, I have never been so deeply into it. I am much more into circuit design.
A few years ago I worked with another engineer who was very much into modeling. He designed a linear regulator which had the nasty habit of burning parts when it powered up or down. That is a case in point indicating a difference between design and simulation. Of course his sims might have uncovered this problem if he had properly looked for it.
Agree, but these devices can help, and they’re not much more expensive than peanuts.
This is my worry with relying too much on simulation. One tiny mistake can result in a pile of expensive junk.
Even if you know simulation forwards, backwards and sideways, can the models always be trusted?
How much time and effort does the simulation require compared to schema. design and PCB layout?
Hobby is one thing, but professional productivity?
In this case specifically, a small signal transistor (such an MMBT4401) was driving a PNP power transistor which was providing the output. If you model it under normal steady state conditions, all looks good. But the input supply is not always present. It will power up and it will power down. Let’s say that normal input is 9V and that normal output is 8V, During power up and power down, the input will briefly be in the range of 7V-8V. In this design, when the input is in this lower than normal condition the MMBT4401 will be driven hard in an effort to get 8V output from the power transistor but that is not possible. The power output must be less than the power input by at least maybe 400 mV. And this design had no intentional means of limiting the current out of the MMBT4401. So during each power up and power down, the transistor briefly experiences high current and also excessive power dissipation. The design might work for some number of on/off cycles until that transistor fails. The “fix” was to simply put a resistor in series between the MMBT4401 and the base of the PNP power transistor.
Yeah, this sort of re-enforces my comments.
Just using a brain to design would probably/possibly include the “what ifs” but simulation will only reflect the input. Certainly more “what ifs” should be featured in the sim. but I think it is easier to become tunnel visioned with simulation.
Ideally, the flow would be design, verify with simulation, verify with bread boarding, commit to PCB.
