Hi, long time KiCad user here. I’m on Linux Mint (using Ubuntu release) and just upgraded from 5.1.2 to 5.1.7.
Basically, I’m trying to export all of my files to JLCPCB without errors or drama! There are a whole bunch of options for BOM export in both Eschema and PCB new. I can’t get a single option to generate me a simple CSV file I can work with that doesn’t contain a bunch of random Chinese characters. JLC outright rejects every file I’ve generated.
PNP is even worse. I’ve found a work around that will allow me to get positioning correct if I don’t panelize and manually correct rotation, but that’s about it.
I’m not the smartest guy on here and I’m really not interested in downloading a bunch of random scripts from Git. Is there anything obvious I’m missing here or are these issues going to be addressed in future releases?
Your issues regarding positioning and rotation in Pick&Place file may be caused by using wrong footprints. You need to verify your footprint centers and footprint orientation “0”. There are standards on it: https://www.7pcb.com/blog/zero-orientation.php (btw: what a nice EDA they do use
This has come up several times…
Short answer: It’s not possible to get rotation right for JLCPCB.
Longer answer: JLCPCB doesn’t respect any kind of standardized zero orientation but expects customer data to be oriented the way the parts happen to be reeled (see https://support.jlcpcb.com/article/99-does-the-red-dot-means-pin-1-in-the-placement-previewer, especially “About the “0” degree for the package”). This means the “0” orientation they expect can be different for different parts in the same package (and footprint), so there’s no general solution.
also note it’s not as critical as you might think. the people at JLC are not idiots and there are humans reviewing every order. if they think you have rotation wrong they’ll contact you, not just pump out garbage. make sure you have pin one visible on the silk and you should be fine.
I’ve used JLCPCB with Kicad (2 times) and Eagle (about 15 times). Rotations are really simple to fix. When you get to the screen where they show you the IC layout in the gerber window, review it. For any ICs that are wrong, go and edit your CPL file to change the rotation, back up two screens in the JLCPCB process and upload your corrected CPL file. Then look at what they think it is. If still wrong, go back and fix it again. If it is right submit it and pay.
And by the way, add the LCSC part number to your symbols and install the plugin referenced in the JLCPCB documentation. You will get a BoM that is exactly what JLCPCB wants. 10X easier than the way I was doing it with Eagle. Makes keeping your schematic in sync with your BoM a snap. Kicad rocks in this perspective.
