I’m getting a design rule check error that pcbnew is letting me create. It seems like a bug but I’m not sure. I have my “Copper to edge clearance” set to 0.5 mm
However, pcbnew is allowing me to place a via closer than 0.5 mm to the edge, but visually it look to be the same as the nearest copper trace. The VIA is throwing a DRC error but the trace is not:
Pcbnew will not let me put the via any closer to the edge than this, but there seems to be a bit of mis-match between the rules and the actual copper diameter of the via as I’m only violating the rule by 0.0005 mm.
This is easy enough to fix manually, but it would be nice if pcbnew prevented the error in the first place.
Application: KiCad PCB Editor x86_64 on x86_64
Version: 7.0.0-da2b9df05c~171~ubuntu20.04.1, release build
libcurl/7.68.0 OpenSSL/1.1.1f zlib/1.2.11 brotli/1.0.7 libidn2/2.2.0 libpsl/0.21.0 (+libidn2/2.2.0) libssh/0.9.3/openssl/zlib nghttp2/1.40.0 librtmp/2.3
Platform: Ubuntu 20.04.5 LTS, 64 bit, Little endian, wxGTK, ubuntu, x11
Date: Feb 27 2023 09:23:58
wxWidgets: 3.2.1 (wchar_t,wx containers) GTK+ 3.24
Compiler: GCC 9.4.0 with C++ ABI 1013