I’m getting a design rule check error that pcbnew is letting me create. It seems like a bug but I’m not sure. I have my “Copper to edge clearance” set to 0.5 mm
However, pcbnew is allowing me to place a via closer than 0.5 mm to the edge, but visually it look to be the same as the nearest copper trace. The VIA is throwing a DRC error but the trace is not:
Pcbnew will not let me put the via any closer to the edge than this, but there seems to be a bit of mis-match between the rules and the actual copper diameter of the via as I’m only violating the rule by 0.0005 mm.
This is easy enough to fix manually, but it would be nice if pcbnew prevented the error in the first place.
Last time I checked pads and via’s were made from copper too.
And if it’s off by only 5um, then it sure appears like KiCad is trying to maintain that distance, but there is a “rounding error” somewhere. If you manually move that via a bit in, and then out again, does it still violate the the margin by 5um? If so, then it may be worth a bug report, or post a simplified example here so other can check, verify and maybe make the bug report for you if you don’t want to do that.
Yeah, if I move out and back it still is off by 5um. KiCad doesn’t let me move it any closer to the board edge than that, so it does appear to be attempting to prevent the error but something seemed off. I’ll report it. I was feeling a little gun shy because the last two errors I reported were not errors, but my ignorance.
If your feeling “gun shy” it’s better to post a test project here first then to post on gitlab. First, it makes it easier for other users to verify, and second, it does not cost any time of the developers, which is a precious resource for KiCad.
