Blind vias triggering hole too close rule violation in KiCad 8

I’m probably doing something wrong again, but a board design that I’m updating in KiCad 8 has a bunch of rule violations that didn’t happen before in KiCad 7.

I’m getting an “Error: Drilled holes too close together error”

As you can see from the screengrab, the blind vias don’t exist on the same layers. I even looked with the 3D viewer to be sure.

Any suggestions on what I might be doing wrong?

Thanks!

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I am guessing this may be a bug in KiCad.

Fun! So it might not be me this time.

Are you interested in creating a bug report for this on gitlab?
You will need a gitlab account to do this.
Alternatively, if you don’t want to do that, you can create a small test project with a few of blind via’s and post it here. I do not have experience with blind via’s myself, but I’m sure there are people on this forum with more specific experience in this area on this forum.

I’m happy to put in a bug report, although it’s probably worth me doing a simple project to test this out too. If it’s anything like the previous issues I’ve tried to report, they evaporate as soon as I try to replicate them.

Please do this. I can reproduce this on 8.0.1rc2.4.
Two overlapped, but not connected blind vias on a trivial 4 layer board. One 1-2, the other 3-4 are flagged as too close. In reality the inner dielectric core separates them

I verified this in a test project, and then created an issue for it:

I was hoping that the OP would raise this, so I didn’t post the issue - like as many users as possible to get comfortable posting bug reports.
I also tries a buried via In2 to In3 with unrelated tracks on the outer layers and this correctly was not flagged as an error

I see a commit to fix this to the 8.0 branch, in what will be 8.0.2. This should be in “Testing” in the next day or two.
Edit
I can confirm that this DRC flag is now working correctly in “Testing”

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