Blind via clearance from irrelevant layer (solved)


I am using Kicad 4.0.4 to design a 4 layer PCB with blind vias. If I try to place a blind via from the bottom layer (B.Cu) to the next closest layer (In2.Cu) with DRC enabled and both relevant layer pairs selected, the via will try to dodge a component on the top layer (F.Cu). This action is superfluous as the hole does not penetrate this layer. Is this normal behavior? I have noticed that this is not the case with uVias.

Could a workaround be to use uVias with hole/pad size set to what I want for traditional blind vias?

Refer to this image (red is F.Cu which the blind via should ignore but instead placement kinks upwards):

I am a moron.

I just noticed the layer pair selection is wrong and it is obvious from the colors shown on the via in the above image.

I hang my head in shame.


Thanks for reporting how you solved your problem. This way someone else might learn from your “mistake”.

I am having same problem using Version: (5.1.2)-1, release build and I can’t find any obvious reasons. I have components on both sides of a 6-layer design. I am trying to place a blind via from Top copper layer to Inner Layer 1 but the via is avoiding an SM component on the Bottom copper layer. See image below.

Just for reference:
On multi-layer boards it’s very easy to get confused in a 2D view, because lots of things overlap.

If you look at the board in the 3D viewer, a lot of confusion can often be cleared very fast. If you:

3D viewer / Prefences / Display Options

and then tun off the “board body” and “solder mask” layers you et partially transparent boards and you can see the layer stack of blind and buried via’s clearly.

Here a screenshot of the Olinuxino A64 Rev_C to give an idea of what it looks like:

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