I am using Kicad 4.0.4 to design a 4 layer PCB with blind vias. If I try to place a blind via from the bottom layer (B.Cu) to the next closest layer (In2.Cu) with DRC enabled and both relevant layer pairs selected, the via will try to dodge a component on the top layer (F.Cu). This action is superfluous as the hole does not penetrate this layer. Is this normal behavior? I have noticed that this is not the case with uVias.
Could a workaround be to use uVias with hole/pad size set to what I want for traditional blind vias?
Refer to this image (red is F.Cu which the blind via should ignore but instead placement kinks upwards):
I am having same problem using Version: (5.1.2)-1, release build and I can’t find any obvious reasons. I have components on both sides of a 6-layer design. I am trying to place a blind via from Top copper layer to Inner Layer 1 but the via is avoiding an SM component on the Bottom copper layer. See image below.