Here is a quick picture of what I have. I have placed via’s where I can so as you can see they can be placed between pads, mostly but there are some places where the tool won’t permit me - there is that big blob in the middle where it will allow multiple in once place (odd in itself but…).
Now hopefully this is due to the fact the cct side isn’t finished but just incase I did something wrong in the constraints… any idea’s?
Without the .Kicad_pcb file it’s hard to see what is going on.
The thin line circles (red for pads, white for via’s) are probably all clearance values.
Clearances may overlap each other, but not pads.
The via between K20 and L19 has a very wide clearance that overlaps the pads.
The via between N19 and P20 has an extremely narrow clearance.
Via’s normally inherit clearance values from the attached net.
You may also have interfercence from copper on other layers, which you have probably turned off.
I’ll just ignore the mess between N20 and M21. It’s not Kicad’s fault that you made a mess there.
Also, if you start laying a track from a pad, then press v for via, then KiCad knows the via is from the same net as the pad, and you can put them closer together if needed.
If you’ve got a single via that has proper placement, then you can align the grid with that via, (Simply: “set grid origin”, then click on the center of that via) and this should help with placing of the other via’s if you set a custom grid with the same spacing as the BGA.
thank you for the reply.
My understanding was that the clearance lines can overlap and this is why it is odd. Right now there were no net’s to the FPGA as it is something I like connecting right at the end by selecting a suitable bank. Presently this was just to make sure the appropriate settings were captured in the to then add “dogbone” via’s to track to inner layers.
I was unable to find a pattern as to why I could place via’s sometimes (with overlapping clearances) and in other places I was unable to (again with overlapping clearance). The mess in the middle is a mess but purely to find some pattern. I am equally surprised the clearance ring around a via has not shrunk when I changed the constraints, but this could be due to no associated net.
What ill do is ill track to the FPGA and try again. if there is still issue ill isolate the FPGA and provide a pcb file. The only thing that is connected to the FPGA right now are
but purely to find some pattern. I am equally surprised the clearance ring around a via has not shrunk when I changed the constraints, but this could be due to no associated net.