BGA symbols and routing questions

[roboya]

Hello!
I have started a new design that needs a MAX10 BGA, 16x16 pads, and I have a few questions about it.

1. Schematic issues:

• Are there existing symbols for a 256 pin device? How can this be practically done? I have seen some schematics with symbols separated in many sections. Can I define a symbol in several sections?
• By the way, are there already symbols for Intel FPGAs?

2. Pattern issues
   I suppose I will have to make a 6 layers PCB. Any comments? From a theoretical drawing point of view, if I use Intel’s recommended patterns (pad diameter = 0.47mm), then if I use 0.1mm traces and spaces, I will need 5 of them (i.e. 2 wires and 3 spaces) between 2 pads.
   So I can route the 3 outer rows of pads to one layer, and all the subsequent sets of 2 rows will need one layer. This sums up to 4 layers, but maybe the center 4 pins can be dropped or momentarily routed to another layer… Anyway, with the power and ground planes, this will require 6 layers. Does this make sense?

Next question: the decoupling capacitors. How to place them? Usually on the FPGA boards I have, they are placed on the other side of the PCB so that they are close to the power pins. But is it “legal” to put a capacitor between 2 round pads? Or do I have to draw a capacitor pattern on top of the pads?
Beside this, assuming I have one ground plane and one power plane, I’m not sure they will all be useful.
Example: in the pin map below, the capacitor between G7 and H7, and the one between J7 and K7 are in parallel, linking 2 ground planes. And they are so close to each other that I wonder whether they will be that useful.
Now what to do with the rows of supplies (labeled with a “o”)? There are a few grounds around, but anyway not enough for eachi pin.

Any hint from experienced users?

Thanks,

Pascal

[jos]

@roboya

MAX10 BGA

That should by useful.

Apart from that. You are lucky since it’s only 256 with a whooping 1mm grid. Should be ok with only four layers. Also suggest try to place only one track between pins. Yep, that means lots of vias.

[kpfleming]

Keep in mind that the symbol (in schematic capture) is for the FPGA, regardless of the package type. The footprint will be for the BGA package. There may already be both available, but as you’ve probably guessed the symbol will be much more complex than the footprint, especially since an FPGA doesn’t have defined usages for most of its pins. You will probably end up having to make a symbol yourself so that you can assign names to the pins which match the functions you are going to configure them for.

[roboya]

Hello!
I don’t think 4 layers would fit because I really need all the pins. As I’m an absolute beginner in the FPGA world, I bought the biggest I found on an evaluation board and I’m using the 144 available pins of the board, as you can see by the compilation result. The 256 pins device has 153 available pins, and if I can use the 5 extra, I will do.

Now one solution would be to use the 484 pin package, but only the outer rows, it will give me more pins. There are 360 available, and the pin rows GPIO counts are as follows:
outer row: 77 pins
2nd row: 55 pins
3.rd row: 62 pins
4 th row: 59 pins.
In this case, indeed, it may be fine with only 4 layers. I have to think about it. And in this case, I could avoid pulling 2 wires between pads. The price apparently doesn’t depend on the package but on what’s inside.

OK, back to kicad related questions:
The capacitors I will put on the bottom side will be between 2 pads, so I think I will use the size 1005. But what about the pattern? Do I have to superimpose a C1005 pattern at the bottom side of the FPGA? Or do I have to create a special FPGA pattern with the FPGA on one side and a few capacitors on the other?

Keep in mind that the symbol (in schematic capture) is for the FPGA, regardless of the package type.

I don’t get it. I’m aware that the symbol and the footprint are 2 different matters. I’m aware that a small op amp can exist in 2 or more packages, for instance SOP8 TSSP8, CASON8, etc, but for instance the max 10M50DAF484C8G has only one package (correct if I’m wrong). Anyway I’m not sure how to define the symbol. Maybe by separating banks, power lines. This would result in 8 items in one package.

Also suggest try to place only one track between pins.
Yes, but in this case, it would mean only one pin row per layer except for the outer most layer which could handle 2, therefore many layers. Is it forbidden by PCB makers? I thought as long as it fits with the maker rules, it can be done.

Thanks!

Pascal

[kpfleming]

@roboya

but for instance the max 10M50DAF484C8G has only one package

Even though that may be true, if five people use this part in five projects (with different configurations of the logic elements inside the FPGA and thus different pin assignments), they’d use five different symbols… but all use the same footprint.

For example, if in your project you’re going to have a 32-bit data bus exposed from the FPGA, with some control lines, you’ll likely want your symbol to have a ‘data bus’ unit which includes the pins you’ve assigned for all of those functions and with names that make sense for that unit. Doing this will make it easier to understand your schematic, instead of seeing 32 data lines and 3-4 control lines all connected to generic numbered pins on the FPGA.