Currently the KLC requires a clearance of 1mm around BGA devices. As i don’t have access to industry standards, i can’t check where this requirement comes from. Does it apply to all BGA devices regardless of size? (1mm clearance for a 0.8x1.1mm device is quite a lot.)
Another maintainer mentioned that the large clearance might be necessary to allow for inspection of the balls.
From that i would guess 1mm is the clearance for nominal density. (In the lib we use nominal density as our guidline.) But the answered question there was about 1mm pitch bga.
The standard that specifies it is IPC-7351B. Here is an excerpt from another site on the subject:
With a small ball size, the placement courtyard can be smaller as less heat is then required to unsolder the BGA component for rework. However, the end user may not plan to rework the BGA if it fails. In that case, there is no need to have a robust placement courtyard, but a recommended minimum placement courtyard excess is 0.5 mm.
Note in that table density refers to ball size, not component placement, although both are linked to courtyard. Part 6 discusses component density and rework considerations (too long to quote).
I guess that the guidelines were designed with large BGAs with many balls in mind, rather than CSP type packages which are much smaller and have few balls.
My guess is that if you use CSP package, you are really wanting a high component density and don’t care so much about rework (e.g. high volume consumer products) (otherwise use QFN/QFP). With BGA, the large number of connections really dictates the need for BGA package, an 1184 pin QFP is not at all practical. However, I didn’t see any guidance related to low ball-count BGAs or CSP specifically.
The goal of the official lib can not be to fulfill everyones requirements but to find a middle ground that works for most. (That’s why i from time to time ask here to get an idea what the community might expect.)
Ultimately, things like chip resistors (caps, inductors etc), BGA arrays and some other footprints would be better to leave to a calculator tool that would automatically generate footprints based on your preferences, rather than having a massive library. I did make one in Excel loosely based on IPC calculator which would generate an actual KiCad footprint file, but it was only for the chip components If you add something like that to KiCad, a native tool that can do all those footprints, you can probably shrink that size of the library by half. Sorry, I’m dreaming here.
W.r.t a tool for creating IPC compliant footprints, have a look at this project (QEDA) which might be of interest. http://doc.qeda.org/getting-started/
