Best practices for power vias on 4 layer PCBs

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The project: I have a bipolar analog circuit on a 4-layer board. Using KiCad 7.0. The stack up is front to back, signal, GND, PWR, signal. There power layer has 2 zones, +15V and -15V. The OPAs (OP27G) straddle the zone boundaries so +V is over the +15V zone and -V over the -15V zone. Each OPA has a set of decoupling caps on the supplies. Currents are nominal 10-20 mA. 30 mA tops. signal bandwidth of interest <200kHz. ICs are SOIC-8 and caps are 0805. The board will be hand soldered.

I’m looking for input/discussion of these two issues:

A) Obviously the decoupling caps need to be close to the OPA power pins. I’m thinking using traces about as thick as the SOIC pads, then placing 3 vias to the power plane in that trace. With a similar strategy for the connection of the cap to ground. I’ll probably use the KiCad default via (hole 0.4mm).

B) If I place the vias close to or in the pads. I suspect the solder will fill the via holes. Is that something I want to avoid. If it is a positive thing, I can put the vias in the pads to make the traces more compact. I fear that the thermal expansion could break the bond between the plating on the wall of the via hole and the interior copper layer.

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One via is sufficient for your decoupling caps.

The worry when placing vias close to SMT pads is “solder thieving.” TCE issues are very far down on the list of things to worry about, so far down that you can ignore them.

Note that OpAmps don’t have the same issues that logic does with respect to power supplies. OpAmps switch so slowly that decoupling is really only done because “it can’t hurt."

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Thanks for the reply. I agree with your statement about the caps being more important for logic. My interest is in ultra-low noise analog. The philosophy is best summed up by Oscar Wilde, "“Moderation is a fatal thing. Nothing succeeds like excess.”

Your mention of solder thieving prompted my to do some research on that. I found a discussion. I don’t think that will be a concern for hand soldering.

I also realize after more reading that I’ll probably have solder mask over the vias unless they are under the pads.

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