I am using KiCad extensively for my schematic design and pcb layout. I have a weird issue with a pull up resistor not working properly on a pcb board made at PCBWay while my breadboarded version of the same design works properly.
Where is the best place to post my schematic and what I am seeing regarding the pull-up to see if any electrical engineers out there might be able to pin point the issue?
thanks
Here would be a good place 
Alternatively I think alot of people use stackoverflow for electronics.
awesome, I’ll post here.
While the users of this forum are typically quite knowledgable in general electronics i would not state that this forum is the best place for such questions. The regulars here understandably are more interested in helping with kicad not general electronics questions meaning the amount and quality of help you might get here will be limited.
So you might really be better off asking your question on https://electronics.stackexchange.com, https://www.eevblog.com/forum/ or even reddit.
The other way round holds true if your question is kicad specific.
I am using a 74LS173 D Flip Flop that has some control lines that may be floating at times before they are asserted. To avoid the control line from doing something I don’t want it to do doing this floating state, I am using pull up / down resistors as necessary to not “assert” the line. For example, on the 74LS173 there is an MR signal that will clear the flip flops if it is HIGH, so that line is pulled down with a 10K resistor.
The strange behavior I am seeing is that my breadboarded version of the attached schematic works as I would expect. If I disconnect the MR line, the 10K pull down keeps the line perfectly low. However when using an SOIC version of the same chip on my PCB, the line jumps to 1V when I disconnect the MR line.
Note I have removed the 74LS245 just to isolate to the 74LS173 and the behavior does not change.
I’ve attached my schematic and the analog capture of the MR line using my DLA.
Also, note the external signal driving the MR signal on the 74LS173 is named CLR on the schematic.
Thanks Rene. I will post there as well.
looking in this datasheet http://www.ti.com/lit/ds/symlink/sn74ls173a.pdf (assuming since you haven’t specified exact partnumber)
The general inputs has a 20K Pull-up resistor (with a Schottky diode in series) so perfect a 1k would be a better pulldown.
LS or HC(T)? This is important. BJT vs CMOS.
Please read the LS specs for low and high level signals. Low requires drawing enough current to pull the input < 0.8V. 1 LS unit load is typically 0.36mA. Multiplied by 10k gives 3.6V, not enough to pull down. But actually the current drawn will decrease as the voltage rises, hence the 1V. Your input then is in an floating state which you were trying to avoid.
BJT TTL does not have high impedance inputs. Use a smaller value like 1k (but this will add to the high level load of the driving gate) or use CMOS TTL which doesn’t require sinking current.
If that MR line is always driven by a push-pull output gate, then there’s no need for pulldowns or pullups. The driving gate should always control the input so it’s not floating. If a manual switch then a different story.
Thanks @Shack and @kenyapcomau. I’ll swap with a 1K and see what happens. I clearly need to be more careful regarding the specific part, whether BJT vs CMOS.
Also, the exact part I am using is the 74LS173AD. https://www.digikey.com/product-detail/en/texas-instruments/SN74LS173AD/296-33969-5-ND/1590385
Woohoo, 1K did it! Now this is the new low value when input is floating.
Now I need to do my homework to understand what I am suppose to be looking at on the data sheet and be able to do that calculation myself.
In general with BJT TTL avoid pulldowns. Pullups are only needed when the input is not always driven or driven by an open collector output. In which case rise time is also affected by the value.
The control signal coming in “CLR” is actually set via a shift register. So basically I disable the output of the shift register, then shift in the value I need and then re-enable the output. The chip I am using is the 74HC299. http://www.skot9000.com/ttl/datasheets/299.pdf
Unfortunately it doesn’t have a “latch output” so I need to disable output while shifting and then re-enable.
Be careful if mixing LS and HC, especially if LS is driving HC. HCT is specifically designed to be compatible with LS.
Guaranteed Ioh = 2,6mA drives now your 1k resistor. So the simplest assumption is you have guaranteed 2,6V as logic 1. I would avoid situations when any pulldown/pullup has to be lower then 10k.
Assuming this data sheet, what am I looking for to tell me the values I need to calculate the correct pull down resistor value for MR?
Read up on unit loads in LSTTL and you can answer the question for any LSTTL gate.
Page 5
Iil(max) = 1,6mA
Vil(max) = 0,8V
R=0.8/1.6=500 ohm.
It is for one IC. If you have 2 ICs each will take 1,6mA so you need 250 ohm.
I have never seen any TTL logic with pull-down resistors.
Do you really need to drive this MR inputs ? What for ?
Do you really need to use LS serie ICs ? Why ?
Driving data lines by 3 state source (few 3 state sources) is OK as their state is important only sometimes.
Driving CLK, Reset and many other lines by source which has moments of being 3 state (Hi-Z) is very untypical (to not say stupid). Being Hi-Z only during Reset is OK. Then before reset state is finished all such signals should be permanently driven.
I suppose these MR inputs could be probably connected permanently to GND.
I don’t see what is the idea of this circuit. D lines go to Q through 2x173 then Q back to D through 245. Going through is not continuous but driven by some external signals.
1.6 mA is for standard (ancient) TTL. LS is just under ÂĽ of that.
You are right.
It was wrong idea to answer at 2 o’clock
I looked for Voltage/Current data and not noticed that there are ICs of two standards in one datasheet.
I hope the rest of my answer is correct.
