I’m really new to this and while I find KiCAD to be really worthwhile, I keep getting it wrong when I make a new component schematic. The “Getting Started In KICAD” doc is somewhat confusing. What should I do first? Create a new directory under the new Project Directory and then Create the component through Libary Editor to save it there? Following the tutorial gets me to create the component, yet when I want to save it to to the myProject.lib folder it saves to myProject-cache. It does not allow me to create the necessary files/folders.
Similar problems arise when I need to add user defined folder paths and add a target library.
Does KiCAD add an extension to myLib.lib that it reads myLib.lib.lib when you make extensions visible in Windows?
All this works, but I feel it to be very messy and I’d like to up my expertise in handling this properly for future projects.
Will The Spice facility simulate correctly on user defined components?
OK. This is solved. Against all fears got my dirty little fingers into it and fell around. There are enough possibilities to get it solved.
The last question about Spice does remain; however; I want to build a cable tester as published in the July 1979 edition of Popular Electronics. I did a distance learning course in Basic electronics (RCA Autotext) but without practicals. I am busy studying Tony Kuphaldt’s Free PDF course as found on AllAboutCircuits. Have built some very small projects, but this is my first real work. Very much want this to work for my Handyman’s business installing access control systems.
The Spice question came up when I first created the MYCONN3 connector in tutorial1. The comment in “Getting Started” was “do not worry about not finding a component, you can create it”. Disregarding Spice, how can KiCAD’s ERC do electrical checks on what appears to be a graphic library file? Where does KiCAD get the information on electrical characteristics for a custom component since there is no way to furnish that to the application?
During the tut, I came across a dialog with several tabs and the one on the far right read Spice. Nice surprise! Homework well done, but this ties in with the first query.
Honestly, fairly, I do not think this has anything to do with Stackexchange. This is internal to KiCAD. Datasheets for chips abound. How do you tell KiCAD the low down?
I have in the meanwhile understood that. The reference to Spice is a tab in the Netlist facility, which specifies a different format for Netlist only. I missed that in getting to grips with the basics, but that’s the kind of mistake I make, so apologies to Joan Sparky.
As said, the matrix of design rules makes sense and I accept that the ERC checks ELECTRICALS only, not chip characteristics. That raised another question in “Getting Started” which is very brief in telling you to mark a pin as Passive. Surely not all can be passive, so where do I find these design rules or do they go on basic understanding? Trial and error? I remain unconvinced that KiCAD would be written on such a shoe string.
I am learning. The curve is steep and hard, but KiCAD is solid, no disappointments. Excellent work.
One other thing. Most likely related. ERC marks as errors all my bus connections as unconnected. Also some PWR_FLAGS although I have fitted junctions all over. Checks on highest magnification reveal no breaks between components and wires. Tried several different ways to connect and wire up, same result. Must be something else I am doing wrong. Some of these got remedied, so it’s difficult to find a line of elimination.
Well said on LTSpice, one of my recent discoveries. Actually very good exercise to repeat the same thing in different modes.
Opened up the Eeschema Help file and will read further to understand the ERC Options dialog. Seems that could help a lot in getting this on the road.
Under Eeschema 5.2 you will ifnd this:-
“Generating a netlist for simulation software such as SPICE.” Looked under that hyperlink but did not find anything directly related to SPICE, but it seems the Spice format in Netlist may just relieve you of all the hard work. This bodes well, similar to the modular differentiation between schema’s and footprints in KiCAD.
Come to think of it, a KiCAD Netlist simulation in Spice would avoid possible input errors AND simulate what you actually built in Eeschema. Less debugging too.
Thanks again for your time. I will just have to knuckle down and do the reading first.
Trick. The wire to bus entries are graphics only. You have to mark wire extensions to pins from different components with the same labels.
The PWR_FLAG issue resolved itself. Learning curve. At first I could not edit those pins like editing the VCC/VDD input/output pins. One has to clearly mark individual components correctly. Did so for a point at random and the error count dropped from some 15 to 4. Common sense really. I see your point on the resistor issue.
Love debugging, but you have to have a starting point. Hate reading app documentation without context.
You’re right on Spice as well. The designer has to do the context/syntax checking.
I do feel a bit of a fool right now, but this is great!! Thanks for your patience. KiCAD’s documentation is excellent. Simple, straight, exact and yet it covers an enormous field of design.
Thank you Andy. This has given me a proper connection to the app.
