I am very new to modern 12mm CPU with ball arrays. Is it possible to make some of the CPU pads a narrow/thin via so that pad is routed to another layer?
Or will the via be blocked by the solder mask?
Thanks
There is not really a reason to not do via in pad for BGA pads except costs and maybe the factor that your board manufacturer can’t do via fill. If you do it you have to make sure the vias are filled by the board manufacturer otherwise you won’t get a good solder connection with the pads.
from my limited experience with BGA I have to say you have to use anyway filled vias, otherwise you can’t place the decoupling capacitors in a reasonable distance to the pads. I usually do the vias in pad not on the BGA pads but only on the (bigger) pads of the capacitors.
You don’t state which BGA CPU you are targeting, but most vendors have the recommended BGA pad, via, trace and escape routing in there app notes or datasheets. I would start there. Intel/Altera have a detailed App Note covering recommended routing for various BGA sizes and pitches I have used in the past, as do other vendors.
Thanks Tojan will find out if my manufacture does filled vias for the few pins I need routed.
And thanks Aaron will see what the STM32MP151 manufacturer provides document and datasheet wise.
According to ST the Packages of those “Can support low-cost PCB down to a 4-layer PTH”
I’m guessing that the “Down to” means this is only applicable to the smallest 10x10mm device
IC manufacturers also know that stuff like via-in-pad and filled vias cost extra, and they try to put their IC into packages where this is not needed.
If you look at the datasheet of the smallest (On page 57):
then you see three dense rows on the outside, a bit of clearance, and a less dense grid on the inner section.
- The outer row can just be fanned out,
- The second row can be fanned out with tracks in the gaps left in the outer rows. 3 tracks in each gap.
- The third row is routed to the center with via’s in the gap between the outer rows and inner grid.
- The pads in the center have enough room in between to put via in between the pads.
It’s almost perfect. The biggest problem seems to be 4 pads of the 2nd row in each corner. I’m not sure how those 16 pads are supposed to be routed on a low-cost PCB.
Can PCB manufacturers make a PCB with a track in between two balls of a 0.5mm pitch BGA?
some can but I won’t consider manufacturers who offer minimum track width/clearances of 0.05mm as low cost as claimed by STM…
[paulvdh] Looking at your graphic of the ball array pins. I think the via in pad is still a good idea as it offers the other side of the board for fanout. So its all a trade off. Routing signals from under the chip has its precision problems but gettings vias in pads have manufacturing problems. Perhaps
a daughter board with the ball array signals fed to the edges like an oversize CPU might be fun. Fun used sarcastically. Think I will have a little lie down.
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