I’m kind of obsessed with footprints. My doctor says there is no cure, and that it is surely a sickness.
So might as well give in. This thread is for anyone who has a really elaborate, nice looking, or otherwise awesome take on common footprints. Awesome meaning if you think your footprint is awesome. This is all subjective, and this isn’t meant to be a thread for judging each other’s footprints. It’s just to share ones you’ve made that your proud of. Constructive suggestions are of course welcome.
I’ll start, here is one of my QFN32 0.5mm pitch footprints. The white and green lines represent dimensional tolerances:
Nice effort! Some remarks / questions about that specific footprint:
Your silkscreen is right under the edge of the component. I used some footprints like that when I started out with KiCad and in my experience it caused issues with reflow soldering (bad connections, shifted components due to silkscreen alignment). Move them outside of your fabrication outline, with offset = silkscreen_tolerance + width/2
I do the same thing for thermal transfer vias (through hole pads in the thermal pad), but I like to keep the stencil paste openings away from the vias if practical. I don’t see how that would work with this layout. Be sure to deselect the solder mask layers.
I’d move the pin 1 dot up, to align with the topmost horizontal silkscreen lines, your current spot is often taken by capacitors and the like.
Recent versions of KiCad allow for a new pad type: ‘rounded rectangle’. Much better fit for all pads shown (nicer balance between spacing and pad volume).
I’ll have a look for some of my footprints I particularly like later, if you want some comparison material.
Sometimes those large thermal pads don’t want to solder as well as the smaller connection pads - especially if you are hand-soldering or using small-scale reflow equipment rather than a full-size oven. In those cases it may be helpful to have solder paste stenciled over the vias.
After soldering a visual inspection of the vias from the back side of the board, with a little magnification, will give an indication of the solder joint’s quality. By looking at how the solder flowed into the vias on the thermal pad you can gauge whether or not the solder paste got hot enough to flow freely, wet the pad, and firmly adhere to the chip’s thermal surface. (Make sure you DO NOT “tent over” the vias on the back side with solder mask - the air trapped in the via will not only prevent solder from wicking into the via, but can also create poor solder joints by expanding and lifting the chip off its pads.)
I can see where that could be useful even on a common D-connector, or a dual-row pin header.
I have used offset pads to accommodate the mounting “ears” on some components. The offset pad is kind of obvious if the ear is supposed to fold over to secure the component, but even if the ear remains straight the offset gives a more secure anchorage and easier access for soldering.
I’d probably put a lot of time into creating an outline like that, and feel proud about it . . . without realizing that the 32 TPI threads on the SMA (or is it 36 TPI?) are almost illegible when the image is rendered at true size.
My reasoning was actually at a similar line of thought. I build my prototypes using hot plate reflowing. This means the heat comes from the bottom PCB layer. Because of the vias the thermal pad actually reaches melting temperature a bit before the rest of the pads, which sometimes makes the PCB leak a bit of solder though untented vias (depending on via size, I’ve had this happen with 0.3302mm holes).
Second rationale for not covering the vias is to create channels under the chip that vent the vias. This way I’ve used tented vias without any problems. This QFN-16_TE footprint shows how in the heating phase the excess gasses have a clear path to escape from any closed vias:
Visual inspection on untented vias generally shows just a little solder drawn in the holes.
I’ve never felt the desire to go and hand solder these kind of QFN parts, but if I would I’d probably create an exposed pad on the PCB backside to be able to solder the thermal pad from there.
I don’t really have a bad-ass footprint, looking over them and trying to find something spectacular, they look all pretty normal to me
The only thing I can offer is a footprint that essentially misuses the stencil service to make me extra thin mechanical sheet metal parts and that I got them to re-adjust the asking price from originally $320 somethings to $32
That was essentially my observation: the solder was usually drawn part way into the via hole and formed a smooth, flat or slightly concave, surface. (A relatively inexpensive 10X toolmaker’s microscope is a fabulous tool for examining these vias.) If I saw a convex “bubble” of solder poking into the via hole, or lumpiness on the solder surface, I concluded “cold solder joint - adhesion is marginal at best” and manually re-worked the part with a pair of soldering irons.
It happened very rarely, but it never bothered me if a little bit of excess solder wicked all the way through the via hole and flowed a little on the back side of the board.
My experience with thermal pads like this is limited to TO-220, DPAK, and SSOP-20 packages - all of which allow you to extend the thermal pad outside the package outline, where you can attack it with a hand-held soldering iron if necessary. QFN obviously requires different tactics.
There is another school of thought with QFN, that says the centre solder density/file thickness should not exceed that of that pads.
ie too much middle solder can hold-up the package, just enough to stop pads wetting.
To help here, I have seen middle Paste areas done smaller than mask areas
So I did an overhaul of the QFN workhorse: QFN-32 5x5 / 0.5mm pitch.
My old footprint was one of the first I did and was a bit clunky: Oversized pads, very narrow paste openings to compensate, a 70% paste area for the thermal pad. All in all it worked, but if a part didn’t solder right it usually was this one.
Objectives for the revision:
Use rounded rectangle pads at the inward side of the pads to maximize clearance to the thermal pad.
Reduce solder on the thermal pad, plus rounded openings (prevent the part from ‘floating’ on the center pad).
Minimize total footprint size (I don’t hand solder these).
Make sure tracks always extend from the pad end (exterior side).
Could you elaborate to what ‘base solder results’ are? My old footprint had a bit too much paste (I had to wick away a bit of solder for maybe 1 in 5 boards), I adjusted this to be more comparable to my other sized footprints and they tend to solder very reliably with a stencil and hot plate.
And I do also have a footprint with a center pad without vias, this is for generic parts (MCUs, power management, etc) that do benefit from good heat transfer. The idea is that this footprint is a good baseline for a prototype. For more refined designs I prefer to use footprints tuned to the design and chip datasheet. The center pad reflects this, it’s 3.6x3.6mm, the biggest size I’ve come across in the wild. Most I’ve seen are smaller though, like 3.2x3.2mm, so an optimized design would have a smaller center pad and maybe extend the rest of the pads inward a slight bit.
Does the datasheet or any other reference for that package recommends the use of Vias?
I mean that it will be possible that the solder past will migrate to inside the Vias and dont produce the expected results.
For the paste layer I like to use 9 square pads totaling about 60% coverage of the thermal pad. This helps prevent shorting between the thermal pad and signal pads. On small QFN’s 4 little square pads also helps them sit flat on the PCB.