Automatically generate a pindefs.h header file for include in firmware project

When we create complicated projects with microcontrollers, normally I define a file named “pindefs.h”, I include it in my firmware project for compiling with main.c. As name suggests, it contains pin definitions, which can easily be used in main.c, have sensible names, and if I change a pin connection, I will only update that file, and code works on the new hardware as well.
eg. of pindefs.h

#define PB13 LED_BUILTIN
#define PC5 SW_USR_2

What I want to do is automatically generate an pindefs.h file from my KiCAD schematic file or netlist.

Has anyone done this already ?
Is this doable ?

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You could process the netlist to get pin numbers and their net name, to get the pin names you would need to load symbol from the schematic library.

It’s doable, not sure how much effort it is worth. Maybe I will have a go if I get bored…

I am trying to do it in python. I just wanted to know if the tool already exists. Do you know of any other EDA tools which do this ?

This is really a interesting use for a Eeschema Python plugin (
I liked the idea, did you put into Git, @DeshmukhMalhar?
Interesting idea: choose the CPU IC and use the I/O pins to create this definition in C / ASM or VHDL (I think is the 3 most used languages?).

Yes. I am currently working on it. I am using kinparse for parsing the netlists. As I have seen that netlists have the information about pin names and pin numbers of a part and the net names and pins connected to the net as well, we can create a table of net name VS pin name, then exclude xtal*, and any pins which have the type power, and maybe passive. thus rendering a table to be used for generating a header file.

The best case can be stated as, if every symbol has a field of part type in it, we can generate headers with generation of netlist in one go.

Current status:
I am trying to extract all nets connected to one part designator, such as all nets connected to U1(say) when U1 is passed in as a parameter.
then I will proceed to build the table a mentioned above.

I need a good name for this project.
I have made the repo for this project public as you have shown interest.
As this is my first python project, I am learning as I go along. Please understand the beginner code and style.

It will be great if this can be incorporated into official KiCAD.



That looks good, but it would be better to parse the XML net list file KiCad generates rather than the “.net” file, especially if you want to make it a BOM plugin. Otherwise the user will need to always run the standard netlist generation before your pindefs plugin.

With recent versions of KiCad, users can update the PCB directly without going via a .net file, so the .net is not guaranteed to exist, or be up to date.

There is an “official” KiCad script to read the XML files,, although it is a bit limited. However, it is quite easy to parse the xml tree to get extra info.

As a little exercise, I wrote a netlist plugin to generate a YAML style output.

# Example python script to generate a netlist from a KiCad intermediate netlist
    Generate a net list file.

    Command line:
    python "pathToFile/" "%I" "%O"

from __future__ import print_function

# Import the KiCad python helper module
import kicad_netlist_reader
import sys

def find_net (ref, pin):
    for net in netlist.nets:
        for node in net.getChildren('node'):
          if node.get("node", "ref") == ref and node.get("node", "pin") == pin:
              return net
    return None

if len(sys.argv) < 2:
    print("Usage ", __file__, "<netlist.xml> <output file>", file=sys.stderr)

# Generate an instance of a generic netlist, and load the netlist tree from
# the command line option. If the file doesn't exist, execution will stop
netlist = kicad_netlist_reader.netlist(sys.argv[1])

# Open a file to write to, if the file cannot be opened output to stdout
# instead
if len(sys.argv) > 2:
        f = open(sys.argv[2], 'w')
    except IOError:
        e = "Can't open output file for writing: " + sys.argv[2]
        print( __file__, ":", e, sys.stderr )
        f = sys.stdout
    f = sys.stdout

# Generate a YAML style netlist

components = netlist.getInterestingComponents()

f.write ('---\n' )
f.write ('components:\n' )

for comp in components:
    f.write ('  - ref: %s\n' %  comp.getRef()  )
    f.write ('    value: %s\n' % comp.getValue() )

    part = comp.getLibPart()
    f.write ('    lib: %s\n' % (comp.getLibName() ) )
    f.write ('    device: %s\n' % (comp.getPartName() ) )
    f.write ('    footprint: %s\n' % (comp.getFootprint() ) )

    pins = part.element.getChild('pins')
    if pins:
        f.write ('    pins:\n' )
        for pin in pins.getChildren():
            f.write ('     - num: %s\n' % pin.get("pin", "num") )

            anet = find_net (comp.getRef(), pin.get("pin", "num") )
            if anet:
                f.write ('       net: %s\n' % anet.get("net", "name" )  )
                f.write ('       net: _none\n' )


It might be best to implement alternative function handling into the future symbol format. (I asked if this is planned back when the symbol format discussions went on on the mailing list but i fear it got lost under the discussion about s-format vs json vs … No matter what i never really got an answer about that.)

I didn’t know about the XML netlist.
I know that user can update the PCB directly, that’s what I have ben doing since it was released, I just forgot.

I just created a new project in KiCAD 5.1.0. I don’t see any XML files in the project directory.

Do I need to update ? Or try nightilies ?

I will study the file you provided and update you soon.
Thanks for reply,
Malhar Desmhukh

Rene_Poschl So, Is there anything planned for it or not ?
what shall we do ?

You won’t until you run a netlist or BOM plugin.

To run those plugins, KiCad does the following:

  1. Generate an “intermediate netlist file” from the current schematic. This is actually a whole netlist, but in XML.
  2. run the plugin as an external command. The placeholder %I is replaced by the full path name of the xml file from step 1)

So for my test script above, it is configured as follows:

OK. thanks.
Now I can see a xml netlist file.
Now, I think I shall do as follows:

  • Use the file you provided to generate a YAML style netlist file
  • Then, use the netlist file to generate my intermediate mapping tables
  • Use the tables for further generating a include file of definitions for C /ASM or other langauges

Does this look right ?


Sure you could do that.

Personally I would generate the C header file directly from the netlist plugin, although having a table might be useful for documentation purposes.

The mapping table would help in debugging the script logic as well, I think.
thanks for reply

Malhar Deshmukh

As i wrote i never got a definitive answer if alternative function support is planned for the v6 file format let alone if it is expected to be implemented in v6 or if that would need to wait for a later iteration.
There are definitely no plans to generate sourcecode from within kicad. This would fall under the responsibility of a script. V6 will add a scripting api to eeschema which should make this easily possible should the alternative function method be implemented. (Something like this has no place in the core functionality of kicad. It is exactly what a scripting api is there for.)

Maybe an explanation why a guy with the kicad flair has no plan: I am responsible for the library not for source code. (I only know about things that are discussed on the mailing list.)

OK. Thanks.
I am looking at netlist for extracting the required data at current stage.

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