When using the ‘automatic placement of selected components’ function, I find two behaviors that are not expected:
Repeating the function does not seem to converge on any solution at all; and,
AutoPlacement ignores the fact that I have used the ‘LOCK’ function to pin the position of some components (such as connectors that I want to be at the edge of the board).
It also appears to not rotate components automatically for best routing…I found some comments about settings in the Footprint Editor that change this behavior:
Would someone please comment on this behavior?
Is there an Auto Placement set-up dialog (I have looked but cannot find it!)
Is there a way to AutoPlace with rotation as the “default” ?
Auto placement is meant to just spread out the footprints to make manual placement easier. It’s not built for optimizing routing so don’t expect too much of it.
No but right click when some items are selected provides “align” menu with some additional options that can help.
Oi.
So this is “auto-distribute”, not auto-placement. Which means, essentially, that it is like running “distribute horizontally” followed by “distribute vertically”, after pushing four components to the limits of the board.
Well, that is disappointing.
And, this still doesn’t explain why running “automatic placement” repeatedly causes items to re-distribute (sometimes with significant jumps). I’ve had a large electrolytic cap jump from the left, to the middle, to somewhere in the right half…then the left half…etc.
Well, “auto placement” seems like a bad name that can give wrong expectations. “Auto distribute” as you mention would be better.
I think actual auto placement is fairly common in other layout software, but I am not aware of any such function that actually works. There are so many competing constraints that goes into placement that the software can’t possibly be aware of.
It’s only disappointing if you don’t take in consideration that placement algorithm that produces actually useful results is on the level of complexity of computer vision problems and likely requires computational power that only big cloud services have with massive machine learning clusters constantly churning data to improve their results.
Expecting your puny CPU to just solve it in a jiffy is a bit much.
In early versions of KiCad, importing the parts into pcbnew simply dumped them into an overlapping pile so the ‘autoplace’ was a significant advance.
Getting placement right is probably one of the most tricky and critical aspects of your layout. It requires understanding of the intent of the connectivity as well as simply achieving the necessary connections. For a moderately complex board, you should expect to spend as much time placing and adjusting components as routing the design - if not more. It’s not simply reducing crossovers etc, it’s ensuring that components are placed for optimal decoupling, efficient routing, fitting specific enclosures and multiple other factors. As @qu1ck points out this is a complex iterative process.
Almost 30 years ago, I used to design Xilinx FPGAs, where the internal block fitting used a genetic algorithm based on net weights. The software was working on a very restricted set of variables and still I had to spend a lot of time tagging nets.
A general purpose PCB is a far more complex problem in size and net description requirements. Designing a circuit requires a much deeper understanding of what a component pin does than the Schematic ERC
Solving this problem is what skilled humans do far quicker than a computer can yet
If your schematic is broken up into hierarchical sheets. It will place the components grouped as per those sheets. So it can give you something close to what your after provided you break up your schematic a little to begin with
Is there any way to lock components (such as a ‘blocking capacitor’) to a component (or to an input terminal, etc) so that it doesn’t float to random locations on its Net?
There is no connection in my schematic across R10, but the network is created with a solid link across the R10 terminals.
There were also bizarre net connections to the Relay.
I thought, initially, that perhaps the Net was following some sort of rules within the PSPICE model but…as near as I can see…there isn’t a SPICE model at all for this relay
How did you do the bold/italic “K1B” and “K1A” notations? Because they are black it looks like you placed them as labels. Unfortunately, that electrically connects all the K1As together and the K1Bs together. If you had instead used regular text annotation they would show up blue, but wouldn’t electrically connect them. Also, your NC, NO, and “Relay_Input” labels, did you use the same labels for the K1A contacts off screen? If so that would connect the relay contact sets, probably inappropriately…
Unfortunately (because there is no way to split formatting), you may have to go without the bold/italic and just go with the labels “K1A_NO”, “K1A_Input”, “K1B_NC”, “K1B_NO”, “K1B_Input”. (I might even use the term “Common” or “Pole” instead of “Input” to better match switch terminology. Especially when I think of a relay input, I think of the control signal turning the coil on and off.)
Would you clarify: Is the behavior of the Labels different if you use Bold / Italic (I thought that choice was entirely stylistic) ?
When looking at the Schematic, I did note that these are called ‘net labels’. I did not understand that they were anything other than ways to label the schematic ‘network’…not affect the functionality of the NET !!
D’oh
Ah ha! I took out the ‘net labels’, re-created the Netlist, and it is now fine. Thanks ever so much for pointing out this error, which I would’ve never found otherwise!
“You learn something new every day, even when you are not trying…”
Make net connections without the need for wires. This is also used for drawing busses.
Label the nets with function for schematic readability (self-documentation).
Make it easy do identify nets within PCBNew for connecting to zones, custom net widths, documentation to the layout person to help with decisions on how to route, etc.
For future reference, KiCad only supports one name per net. So if you have multiple net labels wired together, only one of those labels will be chosen to name the net. There is some priority to decide the name based on the type of label, but of multiple labels of the same type are used it may look random which one KiCad uses to name the net when you go to try to find it in PCBNew.
