Automatic Optimized Parts placement on PCB

Is there some method to place automatically parts from eeschema netlist import, which automatically optimizes parts placements (not only grouping parts as drawn in hierarchical schema pages, more or less putting them alphabetically on PCB not optimized for routing nets) ?

Does some external python S/W plugin exist somewhere ?

Have you tried: Pcbnew / Place / Auto Place Footprints.

I have not used this much myself, but did a short experiment once. It seems worth a try, but don’t expect too much. Proper footprint placement is not an easy task, especially on densely populated PCB’s.

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I can imagine a method that uses the geographical arrangement of the schematic to arrange parts in pcbnew, but I have found that a clearly communicated schematic does not always map well to a fit for purpose pcb layout.
It depends on the use case.
For example, how would this idea work for a hierarchical schematic?

I agree that the abstract circuit view rarely maps onto the physical view of the PCB, but as an initial step as you then begin to figure out how to place items it can be useful.
This is why I extensively use heirachical sheets since you can group by sheet and thus move that group around as you begin to realise an optimal placement

I do not completely agree with this.
For most of the digital circuitry of these days that is true, especially when using labels and buses in the schematic.
For analog circuits, where you use lots of discrete components, using a script to put the parts in (roughly) the same order on the PCB as they are on the schematic is a help with the initial sorting of the footprints, as most of the schematic is likely to have stuff that is in the same net closely together.

A quad pack OPAMP used to realize a 5th order filter has zero visual cohesion between the schematic capture and the PCB placement

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Quad opamps are a bit of a nuisance to layout indeed. Using dual opamps makes this a bit easier.

But even then, all your resistors, capacitors (and inductors?) of your filter will be relatively close to the opamp footprint and each other. The power supply section will be “elsewhere” in Pcbnew.
You won’t put them on the PCB in that order, but it still is a start for the initial sorting round.

Sure they will be close, but they won’t be in positions comparable to the circuit. The primary cause of this is the schematic representations primary goal is to convey the circuit intent and thus the schema used to represent the symbols are totally different:

  • OPAMPS are triangle with inputs on the left and output on the right.

While the PCB layout is more concerned with physical realization and constrained by packaging. Now if every circuit symbol was closer to their physical chip representation then yes such placement at the micro level would make sense but then the circuit would be harder to read (although… auto-routing would be easier …)

A perfect example of this is your typical buck regulator, say… TPS563211

or more specifically:

The circuit orientation make schematic capture flow well and you can clearly see the intent

The “recommended layout”

Night and day difference because there are additional constraints (where the pins are, minimizing loop area w.r.t. switching etc…)

The same goes for analogue, even using dual packages. Sure the parts will be within 1-2cm of each other but that is pretty much their only relationship with regards to circuit and layout placement.

Now general placement to group by macro function… that is useful: PSU block in top-left, FPGA in the middle, ADC type subcircuits on the left, DAC type subcircuits on the right etc…

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You misinterpret the intention of such scripts.
The intention is not to have something resembling a usable PCB layout.
The only purpose for such scripts, is that parts that are close together on the schematic are also close to each other the first time you port them to Pcbnew.
This means the ratsnest mess in the beginning is a lot less, and it lets you easily draw a box around the “5-pole-filter-parts” to start the PCB layout.

It also gives a visual clue of what the parts are, because you know the schematic you designed intimately, and the parts on the PCB are at comparable locations.

So I repeat:
It is NOT the intention to use this for the PCB layout itself.
Just consider that schematics are drawn for readability, so parts are far apart. PCB area costs money, so compact PCB’s are preferred, and PCB’s have lots of other constraints such as parametric capacitance, stringent placement for decoupling capacitors and much more.

It’s just an aid to start with something recognizable.
It is better then just dumping all the parts together on the PCB.
(Ah, those days where all parts in Pcbnew had the same location, so stacked on top of each other on the first import…)

(Spelling correction wants to make a rattlesnake out of my ratsnest)


I totally agree with what Paul said.

On the other hand, I once tried to design a board with several repeated sections which were connected to other repeated sections. The sections were very difficult to place in the pcb, along with the connections. I decided to redraw the schematic resembling the final positions of the sections. After that it was about million times easier to create the layout. But I had to move the sections (hierarchical sheets) manually first which was frustrating. It would have been much easier to get started with the layout if the sections and footprints would have been positioned according to the schematic (which was the purpose of redoing the schematic in the first place).

Well, the sheet boxes are positioned in the schematic, so they could be followed at least in some cases. Inside each sheet the footprints would of course be positioned according to the schematic.

I think we are saying the same thing, but from different perspectives. the Macro placement w.r.t. eeschema would work and hopefully comes when something like altium’s rooms are incorporated (but heirachical sheets already permit initial placements grouped by sheet).

The reason I was holding this stance is there is a script that does placement just like eeschema, it was advertised here and queried about a few times

Quite happy, having created this topic, to read so many and very interesting constructive exchanges.

That will help for sure the community, dealing with more or less same expectations from different industry domains --!)
Capabilities could be extended depending the orientations and effort within the different priorities
whether already possible or expected ones.
Different solutions would be or could always become a reality for the ‘steps beyond’ the existing ones,
or which could be considered as a ‘nice to have’.

Thanks @Paul for your subjection.
We indeed have tried naturally the Auto-placement, upon some others,
by exploring capabilities (embbeded or not),
and offered or not (or differently) in other ECAD ones.


FYI: We are using release V5.1.8/1.

The V6 seems to concentrate the efforts on important expected matters which are nice, such as auto-routing among some others.
In this way, an ‘optimized placement’ could help, while spending less effort to route.

As more or less said,
When the rastnet is not ‘organized before’ in parralell of the schema capture
that should anticipate the ‘step-after’ (even if not its primary objective, among some others…).

a ‘much effort’ will be spent to route, and obviously whith globally less efficiency…

One can also observe the same on less complex design (no to say even on some basic kinds),
delegated to less experienced co-teams for them to improve their different skills,

and with some astonishing unexpected results or blocking points. But this is an other story --!

So this make sense to put part all of these matters and skills into some Python algorithms.

Integrating or not some IA, based on “human state-of-the-art best practices” that are or could/should be shared.

The challenge is informing the placer about critical nets and importantly critical parts of nets eg Vdd power decoupling. KiCad schematic does not have this concept yet

KiCad is open. and could be customized for different users having different needs.

We generate an ‘extended-BOM’ (XL database easily shared and readable by all as a reference input).
with recomm’s to be taken into account for the routing.

Dedicated Fields with specific keycodes could be imagined for an external python process by giving inputs to it (such as top, bottom or dont’ care, parts to be grouped, or generating the NetClasses for pcbnew).

What do you mean David, by the 'a Concept’ that KiCad does not integrate ?

  • Is there some ECAD proposing a better approach (by having some capabilities that KiCad would not offer yet) ?

  • Altium, Eagle, Mentor Dx/Exp, Pads, Cadence Allegro Orcad, Zuken… : have they a better, same or different approach ?

  • Presently KiCad V5/V4 have ‘some pre-placement capabilities’ but not sufficiant enough to avoid this (boring but necessary) placement phase but ‘done manually’ to start the ‘real routing’.

  • Some external python scripts would do at less effort… but haven’t seen any :sob:

  • What could/should be an efficient way which would be better, while satisfying such expectations ?

  • No sure V6 will introduce those matters … ?

  • A 'Better to be re-inforced automatic pre-placement’ (including: parts positions, regrouping, fanout, Net-Classes, power planes and pcb stackup) would help both Routers and Designers, for such repetitive tasks being done when starting a PCB. A machine can do the same much quicker, by taking into account rules (or expressed as wishes or working day-by-day closely with the router) that could be indicated and generated by Design Team in the ECAD during the schema capture, not just before starting the routing…

  • For my DIY projects, the freerouting auto-router will be even more efficient (A good placement gives fast routing, just to finish the last details manually for an acceptable nice finished PCB … !),

  • I’m limiting manual routing (so far necessary) to the critical nets and parts. Most of the time it is fully sufficiant (but spending much on the time on the manual parts placement !).

  • I’m already doing this by using the extended-BOM generated automatically. I’m using presently KiBOM, but the KiCad default one is sufficiant (including or not external libraries from distibutors for KiCad, but stay the same, just additionnal different fields being introduced). Presently done manually (but foreseen to be automated also when adding a part during schema capture, from the libraries…should be probably possible including those fileds as some extentions of the default KiCad’s ones, just get some time to look at it…).
    The step-beyond will be to develop some ‘python scripts’ to accelerate the pre-placement phase as I experimented different placements to get different freerouting quick and satisfying results, finished manually et Voilà! for PCB manufacturing for the ‘next phase’…

  • While expecting V6 would improve such capabilities for KiCad ‘H/W users’…

  • If somebody has some description of the ‘alogrithm used’ in KiCad V5 for these pre-placement capabilities or where to find it.
    That could help to have some ideas when structuring the schema, having experimented different types of schemas and observe the pre-placement, poor results… But perhaps I’m still not using a good approach, not using the full embeded capabilities available in V5, or with some external plugins, that could have been already developped somewhere …???

  • If somebody has some of these …would be quicker for me rather than to develop it (even if it could be some fun for me to do it during my leisure time :blue_heart:).

So far as I am aware V5 and V6 placement has no concept of connection, just ordering on a sheet page.
To make a helpful placer, it would need to be aware of net “weighting” and proximity of decouplers. The latter really need to be in a table, drawing it gets clumsy.

A long time ago I used to use Xilinx 3000 fitting tools, using a schematic input rather than VHDL. This had the concept of net weighting and ran a genetic annealing algorithm to fit. It was a much simpler task than a PCB due to the limited function and interconnection options.

What should be simple and useful would be a simple total of ratsnest length, so that I can try rotating and moving chips to see what minimizes it