I have high-speed nets in which the through-hole via annular ring is only at connected layers. Through most of the copper layers that the via passes through (which have no annular rings), the via diameter is smaller. The copper fill does the right thing and sets the clearance around the via per the fill rules. I want to increase the distance to fill on non-annular sections of the via.
As an example: My vias are 20 mil and my copper clearance is 5 mil. This gives me a total clearance diameter of 30 mil on each copper layer (at connected layers). When the annular ring is removed, the via hole diameter is 10 mil with the same 5 mil copper clearance rule. The resulting metal diameter clearance is 20 mil.
I want to be able to increase the clearance at non-annular layers of the via to be consistent with the connected layer clearance diameter (i.e all via layers to result in the same clearance diameter). Is this possible?
You can omit the condition for net class, or add different conditions suiting your purpose. For further information take a look at the documentation: PCB Editor | 8.0 | English | Documentation | KiCad
This is all I had to do to achieve what I was wanting to do. As soon as I refilled all copper layers, I got the consistent distance around each layer of the vias. Thanks for pointing me in the right direction:
(version 1)
#Rule to increase copper distance on via layers that don’t have annular ring’s