Hi!
I want to isolate the high-current area of the ground plane of my power amplifier, so that i don’t have significant induced voltages in the dsp/preamp part.
(here i’m using a zero-width track as a demonstration)
I can do it by drawing a keepout… Works, but tedious, and looks bad.
I can do it with a track. Track is pretty nice, but it collides with other tracks (on the other layer, i want the split there too).
Any other suggestions?
I usually use two separate pours for similar situations. I put them on the same net, overlap them to connect, and leave gaps between them where I want separation.
I suppose you could make one pour and make the gap part of the pour outline.
You will be able to use for it margin layer if it could be destined to make margin at specified by you layer and not at all layers as it is now.
2 days ago I placed a Feature Request about it:
If you add there a description of your case and vote for it by thumbsup you will increase the chance it will be added to KiCad.
What if you make two different ground names and connect them with a net tie? This is not the same as a necktie.
You can use: PCB Editor / Place / Add Rule Area with the Keep out zone fills setting.
thanks for the suggestion, but i have tried adding some lines to the Margin layer, and it had no effect on the ground planes at all. Am i missing something?
didn’t know what a net tie is… Seems like it is: making two grounds for the two planes in the schematic, and then connecting them with a special custom component that has two pads and a copper graphic connection between the two. Interesting approach, noted. But i don’t see it fit well into my design, as i want the connection be right over the power amplifier chip, which means it should be a pour, not a simple rectangle.
I just drew a few line segments on the margin layer, and nothing appeared to happen. Then I pressed b to re-generate zone boundaries, and a gap in the zone appeared:
doesn’t work. Can you try it on my project? GitHub - DeepSOIC/uberamp1 at margin-cut-test
Application: KiCad x64 on x64
Version: 8.0.3, release build
Libraries:
wxWidgets 3.2.4
FreeType 2.12.1
HarfBuzz 8.3.0
FontConfig 2.14.2
libcurl/8.5.0-DEV Schannel zlib/1.3
Platform: Windows 10 (build 19045), 64-bit edition, 64 bit, Little endian, wxMSW
OpenGL: ATI Technologies Inc., AMD Radeon(TM) Graphics, 4.6.0 Compatibility Profile Context 23.11.1.231020
Build Info:
Date: Jun 3 2024 19:04:47
wxWidgets: 3.2.4 (wchar_t,wx containers)
Boost: 1.83.0
OCC: 7.8.1
Curl: 8.5.0-DEV
ngspice: 42
Compiler: Visual C++ 1939 without C++ ABI
Build settings:
In the Board Settings Constraints you have copper to edge set to 0. Anything else will make it work, with the stated clearance from the edge of the Margin line.
At first it did not work, Then I read eelik’s post and changed that setting and that fixed it.
When I read KiCad documentation I didn’t understood what margin layer is. Then trying it with KiCad V 5 I noticed no effect of margin layer. May be it was a bug in beginning V5 releases or may be it was such in all V5 releases. But later I saw at forum information that it should work and I’ve checked it (being that time at one of V7 releases) and it worked. I don’t use it often but it looks for me that since then it works always. I’m surprised hearing that it not works for you.
Writing it I got the idea what can be the reason - see last paragraph of my Feature Request. May be if you have copper to edge clearance set to 0 and it makes margin layer not working.
I can’t check it at the moment. I’m writing from Win 7 so since V6 I don’t have KiCad here.
Till this moment I was sure that my problems with margin not working with V5 was a bug in KiCad but I just got the idea that may be I had copper to edge clearance set to 0 those time don’t knowing that it affects margin layer working.
Edit.
I see that while I was writing (it always takes me relatively long time, as English is not my first language) the same conclusion was got by paulvdh and eelik and they had a chance to check it.
The constraint affects also the actual edges. But in any case you should use a clearance, the board manufacture doesn’t probably like zero clearance between copper fills and the board edge.
You may also try set this in the custom rules:
(rule "marginclear"
(constraint edge_clearance (min 0.001mm))
(condition "A.Layer == 'Margin'"))
This keeps the board edge intact.
Copper zones should not (almost never!) extend to the board edge. The reason is that the router bit will “smear out” a part of the cut away copper along the side of the PCB while it is routing, and especially on multi layer PCBs (where layers are closer together) this may result in short circuits between layers. I added “almost”, because in some cases such as when edge plating is used, zones may have to extend to the edge of the PCB. But those are rare exceptions.
I have never used custom rules. I thought it would be good to have for my use (like in this Feature Request) margin working precisely to draw it exactly when I want a zone edge to be done and not include expected copper to edge clearance setting.
Didn’t thought it can be done that way. It is interesting that something that I understand as global settings can be set by rules in some sense temporarily (only when margin layer shapes are considered).
But in my case I would like to have such rule integrated in footprint to not have to remember to add it if in 2…3 years I will use this footprint for the next time. So may be it is better to assume typical copper to edge clearance that probably I will use the same in future.
It would be clearer if the copper to margin clearance was set separately from copper to edge clearance.
it absolutely works and is a great solution for my application, thanks @Piotr @eelik !
It’s an accident that i have my copper-to-edge set to zero. Hopefully the board comes out good (i’ve sent it for manufacturing an hour ago, before the fix 
). In any case, chances of having to order a revision are pretty high anyway, it’s the most complex board i’ve ever done yet, and i’m 90% sure there is some serious error somewhere anyway.
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