Anomalous extra space in differential via gap

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I’m routing a high density high layer count board. In my custom DRC I set parameters for my 100 ohm impedance differential vias. 0.1524 mm hold diameter, 0.5 mm spacing (0.3476mm hole_to_hole), 0.127 mm annular width, and ground planes have a 0.69587 mm clearance from the via.

However, when I actually place a differential via pair, and use the X-Y positions to calculate the space between the centers, I get 0.50792 every single time! I know that in the scheme of manufacturing and effect on my board, it’s trivial, but I want to understand where this is coming from rather than shrugging and ignoring it, so here I am hoping someone can shed some light on it.

Here’s my custom rules segment for these LVDS traces.

(rule OuterLayerLvds
    (layer outer)
    (condition "A.Type == 'Track' && A.NetClass == 'Zctrl100'")
    (constraint track_width (min 0.0889mm) (opt 0.1016mm) (max 0.15379mm))
    (constraint diff_pair_gap (min 0.0889mm) (opt 0.10152mm) (max 0.17445mm)))
(rule InnerLayerLvds
    (layer inner)
    (condition "A.Type == 'Track' && A.NetClass == 'Zctrl100'")
    (constraint track_width (min 0.0762mm) (opt 0.0889mm) (max 0.15955mm))
    (constraint diff_pair_gap (min 0.086694mm) (opt 0.20488mm) (max 0.7mm)))
(rule LvdsViaSetup
    (condition "A.Type == 'Via' && A.NetClass == 'Zctrl100'")
    (constraint hole_size (min 0.1524mm) (opt 0.1524mm) (max 0.1905mm))
    (constraint annular_width (min 0.127mm) (opt 0.127mm) (max 0.1524mm))
    (constraint hole_to_hole (min 0.16523mm) (opt 0.3476mm) (max 0.6994mm)))
(rule LvdsViaRefPlaneClearance
    (condition "A.NetClass == 'Zctrl100' && A.Type == 'Via' && B.Type == 'Zone' && B.NetName == 'GND'")
    (constraint clearance (min 0.46708mm) (opt 0.69587mm) (max 1.0933mm)))

This 79.2 microns of extra space happens when the vias are placed vertically, horizontally, or diagonally to each other. The spacing is the same each time (to limits of precision, the diagonal spacing is 0.507920XYZ where XYZ is some string of numbers from the limited precision of a square root).

I have tried setting clearances to absurdly small sizes in the board constraints:

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What am I missing?

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What does that mean? With vias “spacing”, if you mean clearance, is via copper edge to another via copper edge. Hole to hole means hole edge to another hole’s edge. Using your other values in your explanation I get 2*annular_width + spacing = 0.754 mm hole to hole. Using the values I get 2*hole_radius + 2*annular_ring + spacing = 0.9064 mm center to center.

Having deep knowledge about differential pairs combined with deep knowledge about custom rules isn’t a common skill set. The best way to get help may be to attach an example project here (zipped project folder, not just the pcb file!) if you don’t find errors in your original values and calculations.

You can select two items and use Inspect → Clearance resolution to get some information about the actually used rules. It may shed some light to problems.

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Thank you for telling me about the clearance report. I was not ware of that and it does seem quite useful in tracking this down.

As to the 0.5mm spacing question, I want the space between the centers of the vias to be 0.5 mm. The only way I could see to set that in custom DRC was the hole_to_hole clearance option. Since, according to the manual, that is a hole diameter to hole diameter I did 0.5 - 0.1524 and got 0.3476.

I thought I should add, I was examining the clearance report and have discovered the issue / source. The while the hole to hole clearance sets 0.5 mm as the spacing, the differential pair gap coupled with the annular ring size is causing the 0.50792 mm spacing, since Hole_Diameter + 2*Annular_Width + Differential_Pair_Gap is 0.1524 + 0.254 + 0.1052 = 0.50792. It’s trying to treat the annular rings as coupled copper.

In fact, if any of my tests had involved starting at an inner layer and moving to an outer layer with the differential vias I would have notices that the spacing was much wider than 0.5mm since the gap on inner layers is larger. (Apply to palm to face at high velocity).

Anyways, thanks again for pointing out the clearance report, that let me figure out the source of the issue.

Also, I wanted to say, in general, I love KiCAD, sure sometimes bump odd things like this but that’s user error. There is nothing I have wanted to do that the program cannot either do directly, do with a little work in the design rules, or, for impedance calculation, do with a little scripting and plugin development. It’s awesome!

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