Do you know the answer for the following question:
If via has no connection at inner layer then annular ring:
I suppose that never needed but would like to be sure.
I mean sometimes in the sense that may be some (may be old) PCB manufacturing technologies need it.
I just would like to know if by deleting those rings I limit the number of PCB manufacturers that are able to do my PCB or not as this parameter is the same for all of them.
There is not a firm consensus. Some research on the topic: https://cdn2.hubspot.net/hubfs/1871852/Content_for_Degreed.com/Previous_Content/Non-Functional-Pads-Should-they-Stay-or-Should-they-Go.pdf?t=1489525465474
The conclusions are murky, but generally seem to fall on the side of “it’s fine to remove them”, and sometimes even “it’s preferable to remove them”.
I found the article linked to by craftyjon quite clear. Lots of advantages of removing NFT, while the arguments of the naysayers are apparently on a sinking island.
It also reminds me that NFP (Non-Functional Pads) is the “industry term” for these things and is therefore a good basis to find more info.
This link: Should Non-Functional Pads be Removed or Kept in Vias of High-Speed PCB? | PCBCart claims that NFP’s have a positive effect on via strength. But apparently “telegraphing” weakens via barrels (and “telegraphing” is a result of leaving the NFP’s).
But it’s difficult to separate the crud from the facts. Just look at how many datasheets and other sources still recommend to make separate GND planes for analog and digital sections.
I don’t think the question is about what should or shouldn’t be done, I think it’s about what PCB fabricators want us to do or not do.
For example: JLCPCB say the following . . .
but it’s not really clear if that means “you MUST have an annular ring”, OR “if you want an annular ring it must be this size or bigger” so I asked them, they said I can remove the annular rings on the inner layers.
Generally this specification refers to a connected (functional) annular ring.
Ah, the second part of the post:
My best guess is that it does not matter at all, but it’s a guess and I have no real knowledge here.
I read the same from article you linked. I skip reading when they considered 26 layer !! PCBs. I have recently started to use 4 layer and got a question from PCB manufacturer through contract manufacturer: "Isn’t it a mistake that you have nothing (except annular rings) at In2 layer. I answered that unfortunately I couldn’t order 3 layer PCB 
It is hard to imagine what for I could need 26 layers.
The argument that deleting NFP helps to avoid shorts can be true only if NFP are removed by PCB manufacturer and not if I remove them myself. If I remove them zone fills will be recalculated and come closer to holes, I think. I have never tried to delete NFP. Now I am considering it. I don’t know if after deleting Unused Pads I will have chance to get them back (other than using backup PCB copy).
My guess too.
I think that all manufacturers drill holes after all layers are put together. I suppose that drilling and plating is made before external layers etching, but I’m not sure. I suppose that external layers have to be continuous for plating as I think it is electrochemical process. I’m not sure of it and I didn’t searched to find it. So I think that internal layers need not to conduct current for plating so annular rings at internal layers have nothing to it so if they are left or removed is indifferent.
If etching takes place after plating than annular rings at external layers are mandatory to protect plating from being etched. But I don’t know if my assumptions are correct.
I’m quite sure about that. The alternative is drilling holes and then putting prepreg and more copper over them. That is an extra step and thus costs extra money. These are called “buried via’s” and are not visible on the outside. It’s also byond your intended use of a 4-layer PCB.
I am quite sure.
Plating the holes is an electrolytic process (they fist make the holes conductive to get it started, some kind of carbon dust or paint). The electrolytic process needs an electrical connection, and that is very difficult after etching. So normally the inside of vias is plated and the copper thickness is grown from 17 to 35um in the same process step. Eurocircuits has some nice video’s about the PCB production process. Either JLCPCB and/or PCBway too, but there are probably more youtube video’s.
The via’s must be made conductive on the inside after the drilling before the electrolytic process can begin. During the electrolytic copper thickening the whole PCB is just a single elecrode
This is a step where my knowledge is lacking. I do not know how they plug the holes so the insides of the via’s do not get etched.
I supposed that what protects copper tracks from being etched can also protect pads (including THT pads) but it is not so obvious how and if it is possible.
Tracks are made robust for etching by some photo process. May be the photosensitive film is solid enough to cover small holes or at least its plated walls.
The photoresist they use for selective etching needs UV light to develop, and that would be difficult to develop inside the vias. A guess would be to fill the holes with some kind of hot wax that bet melted out again later.
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