Many newer parts are using WLP (Wafer Level Package) packages. Some have solder balls as small as 7.1 mils (diameter) with center-center pitch of 0.4mm. These require traces as narrow as 2.7 mils with 3.0 mil spaces inside the footprint.
I’d like to have a “different” set of design rules over the package area of the PCB, where “fine” lines are necessary. After breaking out the signals, “coarser” design rules are appropriate.
So right now, my options are:
Use the “fine” design rules everywhere. Design rule checking will “work” everywhere, but there may be places outside the WLP footprint where signals are closer than I would really like them to be.
Use the “course” (or regular) design rules and put up with violations within (and perhaps very close to) the WLP footprint. These would have to be manually checked any time a change is made to the layout.
The current workaround for KiCad is to use net-ties. for this.
A net tie is a short piece of PCB track that is used to connect 2 nets with different labels. With it you can connect the part with the fine rules to the part with the coarser rules.
So far it is not possible. I’m doing like you with power circuits: I need the “normal” clearance for the control stuff and a big clearance for the power lines.
I think it is in the v6 roadmap, but I’m not sure whether it is only a feature request.
I’m not doing it but as I understand the idea is to put all nets connected to that IC to separate NetCalss and define different rules for that NetClass.
I believe my “net-tie” magic word was too short an explanation.
A possible way to use net-ties:
First do a partial board layout, so you know which area is of interest, for example a single BGA ic.
Draw an imaginary circle around your BGA.
Any track that crosses the circle gets a net-tie.
All net ties are placed on the circle edge.
This effectively splits all those nets in 2, and you can use different rules inside and outside the “circle”.
Workig with net-ties in the current KiCad is a bit of a kludge. Alternatively you can use some fine design rules to break out the BGA, and then set the rules wider for the rest. This will generate DRC errors around the BGA as long as the coarse rules are active.
Also, changing those tracks to different rules is cumbersome and error prone. It’s probably easier to define a few rules which are used for this, and then manually change the clearance and track with settings for these few rules when working on the BGA part.