"Align to grid" issue with EAGLE imported project


[In following description I care only about schematics, there is no PCB layout involved]
[KiCad 7.08 was used]

I’m struggling with wires alignment when trying to add nets to project imported from Eagle. You can freely download it here. I think that it was created automatically by some bitmap-tracing script, but it loads successfully, both in Eagle and Kicad.

The first problem is that not all wires are aligned to grid. I try to fix it by Select All (CTRL + A), then RMB → Align to grid. The problem is that after that, transistors are disconnected from the wires, as in the image below:


My questions are as follows:

  • Is it issue with the way that KiCad handles alignment, or the Eagle project that I use?
  • How can I fix it in a simplest way?


same transistor before the Align to grid step (note that base wire is not grid-aligned):

the transistor symbol is drawn with a much smaller grid than your grid used in the picture.
You could try to reduce the grid-size (View–>Grid Properties) until the connection-points (pins) of the symbol also aligned to the grid.

note: this is only a workaround, for normal usage one (especially a kicad beginner) should stick with the recommended 0,05"==50mil grid.

thank you, that’s very helpful! for that particular use case the grid size reducing will work for me. i was thinking if it’s feasible to make it programatically (iterate over all transistors in Eagle .sch file and round their dimensions to 50mil), but I don’t know the .sch format to know if it will still work - it depends how the connection information is kept - A is connected to B if their coordinates overlap? if this is the case, then programatic way would not work (we need something like name-reference). Anyway, thank you for the good idea!

For me it looks like transistor having pin ends in 1/2 of grid shown at screen-shot.

I’m the creator of the Eagle project you’re attempting to import into KiCad.

For those who haven’t looked, this is the complete schematic for the Intel 4004 CPU. It consists of 1807 4-pin MOSFETs and 435 resistors, all on a single Eagle schematic sheet. It was generated by processing the bitmap schematic and netlist files that are part of Lajos Kintli’s 400x simulator to produce a 40189-line Eagle script. The schematic contains attributes that identify the location of each component in the 4004 silicon die, and all of the components and nets are labeled with the same names as found in the simulator.

To be able to match the positions found in the simulator’s netlist, I created custom MOSFET and resistor symbols on a 25 mil grid. The MOSFET symbol measures only 225 x 350 mils, and the resistor symbol only 100 x 375 mils. Even so, printed on a 1:1 scale the schematic would be 100 x 80 inches.

Personally, I would just tell KiCad that it’s a 25 mil schematic rather than trying to convert this to a KiCad-standard 50 mil grid. Edit → Grid Properties

The Eagle schematic itself correctly identifies the grid distance as 25 mils:

<grid distance="25" unitdist="mil" unit="mil" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>

Perhaps KiCad’s Eagle schematic importer doesn’t know how to process this attribute? I know KiCad has problems handling net names that don’t have a visible label attached.

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huh, having the schematics author replied to my question is last thing that I would expect! That’s pretty cool.

Leveraging the fact that I have your attention, just wanted to say that in my spare time in following months I will be working on documenting 4004 design. I think that it can be a good teaching material, as high resolution die photos are available, and so is the importable schematics. So be aware that your work is proved meaningful and is being continued :slight_smile:

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I’m in the process of writing a book tentatively titled “Deconstructing the Intel 4004”.

There are several histories that cover the architecture design by Ted Hoff and Stan Mazor, and the silicon implementation by Federico Faggin and Masatoshi Shima. But there hasn’t been an analysis of the logic-level design. That’s where I’m focused, including the implications of using dynamic rather than static logic, which is an unfamiliar concept to many EEs. At this point I don’t expect to get down down to the construction of individual transistors except where it affects the higher-level design, like the implications of using pass transistors and the necessity of bootstrap loads. Faggin’s books do that far better than I could ever hope to.

Are you aware of my blog? Insanity 4004

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@RRPollack Are you already aware of:


Klaus and I corresponded during his work to create this replica. Like all good engineering, his work built, in part, on my efforts. Just as mine built on the research by Tim McNerney, Lajos Kintli, and others. Which built on the original work by Federico Faggin and Matsatoshi Shima.

To quote Issac Newton, “If I have seen further it is by standing on the shoulders of Giants.”