Hi.
I’m trying to add slots between the pads of a TO-220-3 footprint using lines on the Edge Cuts layer, which appears to be the recommended approach.
DRC produces “Board has malformed outline (not a closed shape)” errors.
Is there anyway to avoid the errors or should I just exclude them?
Thanks.
Slots should be drawn as two lines connected by two arcs, not just a thick line.
Or draw a rectangle and do Right click → Shape Modification → Fillet Lines…
Or you can convert thick lines to a polygon using Right click → Create from Selection → Create Polygon from Selection… and the “Create bounding hull” option
Not a good idea. Edge cuts are defined by center of lines (width of lines at Edge cut layer have no influence on PCB size). Such straight line section is only a line - don’t defines any opening shape.
Thanks to you both for your replies.
Allowing a reasonable pad width minus hole diameter won’t seem to accommodate JLPCB’s minimum slot width of 1mm AND edge clearance of 0.2mm.
I have a commercial PCB on which the slots seem to be 0.75mm or 0.8mm wide. I’ve gone with 0.75mm here.
What are the slots for? Insulation? Air cooling?
Looks like holes for the metal tabs on a socket
The slots are for insulation.
So you don’t trust the insulation properties of soldermask and FR4?
The TO-220 device is a high voltage MOSFET switch in a flyback converter. According to the simulation at least, drain to source switching transients could exceed 600V. Off-state Vds is around 480V.
Are you working to some standard or datasheet recommendation, or just guessing? There are people on this forum who know the specs, not me.
Good question!
There are various recommendations around but IPC-2221B conductor spacing requirements suggests external, un-coated conductor clearance should be 2.5mm for 500V.
The TO-220 package doesn’t even provide that between the pins so 2.5mm is conservative.
My TO-220 footprint with narrowed pads only provides 1.2mm between the pads so a slot is required.
In addition, I have an MPS evaluation board with similar voltages and it uses slots.
Then change the board manufacturer.
Personally I wonder their 1 mm minimum requirement. They can do 0.5 mm plated slot, but not < 1 mm non-plated? And what’s their minimum inner sharp corner? The edge is made with a router bit and so is an inner slot. Usually everything has some explanation, but I just can’t see it here.
EDIT: PCBWay has this:
Plated slot ≥0.5mm
Non-plated slot ≥0.8mm
So there must be something in the manufacturing process which causes this, but I don’t know what it might be.
EDIT2: And, BTW, you could consider making the slots part of the footprint using just NPTH pads, not edge cut outlines.
Thanks for that suggestion. I’ll do that.
I just put the gerbers into JLPCB’s quoting tool and it didn’t complain about the slot being < 1mm wide.
You will find that most manufacturers TO-220 drawings don’t even specify the lead spacing near the body.
Breakdown voltage on PCBs depends on the pollution levels.High voltages need conformal coating.
According to what I remember from EN 60950-1 for the same voltage creepage have to be higher than clearance. If clearance and creepage are equal creepage is what limits you. Making slot you increase creepage enough to reach limit set by clearance.
I guess it’s a machine time issue.
Slots in pads are usually small (a few mm) and slow movements needed for small mills are not a big issue. But when routing bigger sections, it does become a time issue, and with a thicker and stronger mill, routing can be done faster.
Datasheets usually do have a mechanical drawing, and TO220 is pretty much the same regardless of the manufacturer. In the picture below, the pins can be up to 1.4mm wide right at the body, and with a pitch of 2.54mm, that leaves 1.14mm clearance.
Because of this, it does not make much sense to mill isolation slots between the pins on the PCB. Alternatively, TO-220 has quite long pins, and the pads do not have to be that close together. In the AKL (Alternative KiCad Library, installable with the P&M Manager) there are several TO-220 footprints with staggered pins.
Thanks for finding a drawing showing the base of the lead, I checked a few without this. A pity that they don’t dimension the gap as the tolerances add up.
If you depend on a slot for clearance, you had better be sure that it cannot get dust and other contamination in it.
Staggering the leads is a better solution, even if the part is flat.
Thanks. I wasn’t aware of the Alternative Kicad Library. The staggered footprint looks good.
