I would like to create a library footprint for my high speed AC coupling caps for differential pair signals that includes a rule area (keepout copper/via/pad) for one specific inner layer, that is, the ground plane underneath the parts on the top signal layer, in accordance with recommendations for high speed routing. Whilst this is possible in the PCB editor, in the library footprint editor the layer choices are only top, inner, and bottom. How to create that rule area for only one inner layer in the footprint editor? Fiddling with every instance of capacitor in the PCB is going to be hugely annoying. And since this is a 10 layer board, voiding on every inner layer is not acceptable.
I don’t have KiCad open, but this should be possible with a project custom rule. Let the keepout be without the “disallow” rule in the footprint. Write a rule using layer clause and set disallowing there.
I don’t know whether your goal has a good cause, but I also don’t know everything about (high speed) PCB design.
Using specific inner layers in a footprint is problematic because footprints are supposed to be project independent, so number and names of internal layers are “unknown”. I did a short test and KiCad does not complain about two rule area’s with the same name, so that’s a plus for you.
I don’t know how critical the size of your rule area is, but you can also use the courtyard area inside custom rules.
I was wondering how to use the custom rules for that since I’m already using custom rules for diff pair routing purposes on different layers. So the rule would need to select a particular footprint name. Using the courtyard as the shape for the area would work as the voiding guidelines generally are 0.1mm larger than the pad area. Using smaller parts helps, voiding is optional using 0201 and smaller parts but not everyone can handle parts that small. Voiding is required for 0402 and larger parts when routing PCIe Gen4. Goal is to minimize the capacitance to the reference plane underneath the AC coupling caps.