Accelerated graphics very slow?

Layout
1

Hi all,

Im trying to route a PCB and for some reason whenever I press X (route a track) my kicad freezes for a couple seconds. I have a strong PC (RTX 4070 Ti Super) 32 GB RAM etc so I dont think this should be happening on a light to medium sized board. Any advice? When I’m in fallback mode there is no problem.

Kicad Info:
Application: KiCad PCB Editor x64 on x64
Version: 8.0.6, release build
Libraries:
wxWidgets 3.2.6
FreeType 2.13.2
HarfBuzz 9.0.0
FontConfig 2.14.2
libcurl/8.8.0-DEV Schannel zlib/1.3.1
Platform: Windows 11 (build 22631), 64-bit edition, 64 bit, Little endian, wxMSW
OpenGL: NVIDIA Corporation, NVIDIA GeForce RTX 4070 Ti SUPER/PCIe/SSE2, 4.6.0 NVIDIA 566.03
Build Info:
Date: Oct 14 2024 01:02:33
wxWidgets: 3.2.6 (wchar_t,wx containers)
Boost: 1.85.0
OCC: 7.8.1
Curl: 8.8.0-DEV
ngspice: 43
Compiler: Visual C++ 1939 without C++ ABI
Build settings:

cheers
dom

2

Hi, please give OS and Kicad version.
Find them on Kicad > Help > About Kicad > top RH corner Copy then Paste into a forum post.

3

Thanks for the reply, I edited OP with the requested info. I noticed it also freezes when I’ve completed a track.

1 Like
4

Thanks.
I’m not sure of your problem, but I doubt anyone else would give an opinion without that information.

5

Where did your graphics drive come from ?

  • installed by default with Windows 11
  • from the PC vendor
  • direct from the Nvidia website

?

6

Came from nvidia website. Havent had any issues with any other graphics intensive applications.

7

I think it might be related to my custom DRC rules. Has anyone seen this make a significant impact? Here they are:


(version 1)

#
# EuroCircuits 
# Defined impedance 4 layers, 35um inner copper
#

# board edge clearance outer copper
(rule EdgeClearance
	(constraint edge_clearance (min 0.25mm))
)

# courtyard 0.1mm exception
(rule CourtyardClearance
	(constraint clearance (min 0.1mm))	
	(condition "A.intersectsCourtyard('*') && A.Type != 'Zone' && B.Type != 'Zone'")
)

(rule "Allow vias of same net to intersect"
   (constraint connection_width (min 0mm))
   (condition "A.Type == 'Via' && B.Type == 'Via' && A.Net == B.Net"))

(rule IPI
	(constraint hole_clearance (min 0.20mm))
)

(rule OTW
    (layer outer)
	(constraint track_width (min 0.1mm))
)
(rule OTT
    (layer outer)
    (condition "A.Type == 'Track'")
	(constraint clearance (min 0.1mm))
)
(rule OPP
    (layer outer)
	(condition "A.Type == 'Pad' && B.Type == 'Pad'")
	(constraint clearance (min 0.1mm))
)
(rule OTP
    (layer outer)
	(condition "A.Type == 'Pad' && B.Type == 'Track'")
	(constraint clearance (min 0.1mm))
)

# pad to via clearance 0.1mm
(rule Pad2ViaClearance
	(condition "A.Type == 'Pad' && B.Type == 'Via'")
	(constraint clearance (min 0.1mm))
)

(rule ITW
    (layer inner)
	(constraint track_width (min 0.125mm))
)
(rule ITT
    (layer inner)
    (condition "A.Type == 'Track'")
	(constraint clearance (min 0.125mm))
)

(rule ITP
    (layer inner)
    (condition "A.Type == 'Track' && B.Type == 'Pad'")
	(constraint clearance (min 0.125mm))
)
(rule IPP
    (layer inner)
    (condition "A.Type == 'Pad' && B.Type == 'Pad'")
	(constraint clearance (min 0.125mm))
)
(rule IVV
    (layer inner)
    (condition "A.Type == 'Via' && B.Type == 'Via'")
	(constraint clearance (min 0.125mm))
)
(rule IAR
	(layer inner)
	(condition "A.isPlated()")
	(constraint annular_width (min 0.125mm))
)





(rule RF_width_outer
	(layer outer)
	(condition "A.NetClass == 'RF'")
	(constraint track_width (min 0.185mm) (max 0.185mm))
)

(rule RF_width_inner
	(layer inner)
	(condition "A.NetClass == 'RF'")
	(constraint track_width (min 0.158mm) (max 0.158mm))
)

(rule SAI_inner
	(layer inner)
	(condition "A.NetClass == 'SAI1'")
	(constraint track_width (min 0.10mm) (max 0.25mm))
)