nice article…
anyway the ways to create thermal vias have pros and cons…
one solution could be like the following picture from the same article
but in my prods I used the TI suggested one, with drills of the suggested dimension, as per specific chip doc…
Hi maui,
I’m new to QFN packages, but an old friend of mine (that recommended the article) is using them a couple of years and have warned me about possible issues.
I also used to follow the footprints provided in datasheets, but in case of QFN, following them can cause some issues. For example, following the TI datasheet’s recommend stencil will inevitably left some pad vias exposed to solder paste.
So, depending on the amount of solder paste that were applied two problems can arise. If the solder paste layer were too thin then your board can end with voiding as showed in the Rx below:
In the other hand, if excessive solder paste where used, then you can have problems with solder wicking variability:
Or can be a bit worse and end up with solder protrusions on the pad vias as stated in the image bellow:
I played a little bit and created a footprint using smd 10 pads with F.Past layer only.
I will try to use it in a new prototype soon after receive the board manufacturing ok first, of course 
for that reason I used what TI suggested…
so what your friend is suggesting as a solution (not just the warning)?
The company that he is working is using the SMD Window design suggested in the article.
Are you using a footprint with 25 via holes (0,3mm) and a stencil with 9 squares of 1,45 x 1,45mm ?
Yep, that is what this research is recommending…
humm I didn’t use any solder mask over the main EPad… (I mean the main EPad was free of mask, copper in view)
In your chip is there a big pad connected to vias? I don’t see it on your first picture
Seem that you are using the common current practice “option 1” below:
[quote=“maui, post:17, topic:5293, full:true”]In your chip is there a big pad connected to vias? I don’t see it on your first picture
[/quote]
That is the chip I’m about to use:
Let us know how things go when you do another run. I guess leaving the solder mask within the pad helps prevent migration of the solder (especially down the vias) but shouldn’t otherwise interfere (typical soldermask thickness = 0.012mm). Typical manufacturer recommendations I’d seen suggest that a 30% contact surface is what they aim for.
Looking at all those pictures… in the end the solution will be to have a raster of BGA like solder pads interleafed (half pitch) with a grid of vias.
No messing around with special pad shapes etc.
Just make the BGA thermal contact pads as big as you need to get 50% contact area and wetting/contact should be no big deal as the gas/air can escape into all directions.
Something like a 2D NaCl crystal cage.
Maybe the pads can even be simple squares, to get more thermal conductive area out of it (45 deg rotated).
Anything more complicated than that is begging for trouble IMHO.
Those X-Rays look like air/gas trapped within the solderpaste and not being able to get out during reflow.
I think that those pictures alone without a good context maybe do not reflects its real purpose, perhaps would be better read the article where they came from. There you will find more complete explanations. 
an other nice doc about it
http://www.smta.org/chapters/files/Heartland_Heartland_May_2015_BTC_DaleLee.pdf
How do they say, an image is worth more than 1000 words…
To bad the new pad shape of rounded corners (fillet) doesn’t allow chamfered edges…
Or alternatively an octagon as basic shape with round corners 
When there are vias within the thermal pad i’ve found that a large amount of the solder paste goes through to the other side of the PCB which can cause problems - to stop this putting solder resist over the vias works well but printing over the solder mask can lead to voiding.
One solution when the vias have been masked is for the stencil to be designed to avoid the mask areas as shown below
See article - http://www.surfacemountprocess.com/a-guide-to-effective-stencil-design.html
I’m new here (just download KiCAD tonight), and I came across this post trying to learn the ropes. I had been using EAGLE for work, but I’m not a fan of what Autodesk did with it. I can’t offer much in the way of how to do it with KiCAD, but I thought I’d offer my two cents from an assembly standpoint. Briefly, I’ve been designing PCBs professionally for four years, and I’ve been through the issue of thermal vias in pads many times in my work.
There are a lot of answers to this question, but one thing to consider is how hard you plan to drive the chip. If you aren’t going to be pushing the chip to its limits then you may not even need thermal vias. Check your datasheet for thermal information before taking this suggestion. I always prefer to design them in… just in case. Another thing to consider, as others have mentioned, is how thick are your various layers of solder paste, solder mask, etc. One thing I did not see is to make sure that your board house can actually build it. There are minimums that they can have for spacing between copper pads, pad edge to mask edge, mask thickness, trace thickness, etc. I’ll try to find some good references with more details on this, but that’s how board houses charge. They’re not willing to give it up lightly. Generally, the more lax your requirements are the cheaper the board.
Speaking specifically about vias, as you showed in mid Feb there are several options such as tenting, copper plating, etc. My experience is that tenting and plugging do not add anything to board cost. When you start adding more conductive material, it can be an enormous charge. The most cost-effective way I have found thus far is as follows:
Use a solid thermal pad on the copper layer. Create a cross-hatched pattern of solder mask OVER the thermal pad. Use two strips of solder mask in both directions which divides the pad into 9 equal parts. Place four thermal vias in the four intersections you created with the solder mask. As far as the paste layer, I’ve seen a lot of suggestions, but the type of finish you have can have an impact on this. I’ll explain that in a second. I would suggest making the paste layer a few mils in both dimensions smaller than the remaining exposed copper. I’ve seen anywhere from 40 - 70% as being acceptable. When you have your board built, ask for tented or plugged vias.
The finish of your PCB may also have an impact on the solder coverage percentage. A PCB finished with ENIG (immersion gold on nickel adhesion layer) will have a smoother surface, and it is preferred by assembly CMs because it improves solderability and shelf life. It is also more costly. If you are buying this from your own pocket you might opt for a HASL (hot air surface level) finish, but this will result in a much rougher surface. For a few boards it wouldn’t be as much of an issue, but if you plan on running 100s go for gold. My gut feel is that with a HASL finish you would want closer to a 70% solder coverage, or at least a thicker solder paste layer.
I apologize for the novel and the lack of pictures. Like I said, I’m new to KiCAD. I know a picture is worth 1000 words, so I will try to get a footprint put together this weekend. I hope this helps (even if a little late).
The article referenced by OP is very good. So good in fact, it bugs me to see it suggested its origin is some obscure content-scraping copycat clickbait ripoff blog BS.
The article was formally published in the March 2016 issue of PCD&F / CA, a (horribly named) trade magazine. It is freely available from their archives (up to 2019) here for online viewing and also as pdf download.
Since 2019, issues are hosted here
Topic is from 7 years ago
The magazine link is genuine
