Is there any way to get help in assigning identical units to different package units more dynamically?
Concretely, I have a schematic with 6 similar opamps (tl07x) which I would assign to different package units - so I have a TL072 and a TL074, 2 + 4 opamps.
My current understanding is that I need to associate these already in the schema and therefore limiting my options when laying out the board. Even if so, is there any nice workflow tips around this so I don’t have to clicketiclick so much when I change them around after doing a bit of layout experimenting?
What really limits your options is the footprint of the chip. And yes, if you want to use a different opamp, let’s say 3+3 instead of the previously selected 2+4, you need to go back to eeschema, make the changes, redo the netlist and load the new netlist into pcbnew (layout editor).
What really limits your options is the footprint of the chip
Yes, but also if staying with 2+4, if there was a way to make the software understand that these 6 opamps are the same and can be allocated to any of the units without leaving pcbnew - that would be really helpful.
Now if I realize that opamp X should probably be in proximity to omamp Y instead of on that other chip way over there, I need to go all the way back to the schema.
KiCad abstracts between schema and pcb layout which is great, but I’d really would have loved if one could abstract even further. Just saying I have these 6 opamps of type X and do the unit allocation when designing the pcb (where I think it belongs)
I’m afraid connections are made pin to pin and not chip to chip. After a satisfactory positioning of the components in the layout, the way back and forth eeschema-pcbnew could be done only once. Good luck!
Of course, behavior like this would require a way to get the information about swapping units out of PCBNew, into the netlist, and update the schematic.
Some PCB layout software allows you to exchange units within a package but I don’t recall ever encountering one that could exchange units from one package to another. I agree it would be a useful capability in some situations but I suspect it would significantly increase the software complexity of the program.
Playing Devil’s Advocate:
One could also use 2 TL074 and terminate the unused pins on the unneeded op-amps.
1)One less total chip parts.
2)One less total bypass caps.
3)Two less paths to route for power and gnd.
4)Less sq-in of board space if the traces can be routed inside the footprint to the next op-amp (both top and bottom layers).
@Andy_P I think your advice is also solid. However, I believe that the right solution depends upon the exact individual application.
I am not a big fan of quad opamps. Unless some of the sections are used in very simple circuits (e.g., non-inverting buffers), there never seems to be enough PCB area near the package to place all of the passive components. And, there are many more varieties available in dual packages than quads.
Or if your design has a lot of op-amps. A recent design of mine uses 36 op-amps, that’s 9 vs 18 packages, and the dual packages aren’t half the size so they would take significantly more space. Often you can even get the quads in a TSSOP package making them almost identical in size to the dual. The discrete components are available in sizes that make it less difficult to place them in the vicinity of the quad package.
A long time ago, there was a PCB CAD package called P-CAD, which was subsequently bought by Cadence. In that package, when you created the PCB part, you told the software if the units inside were interchangeable, and if pins on the individual units were interchangeable. For example, SN7400 (Quad, 2-input NAND Gate). This device has four interchangeable gates with two interchangeable inputs each. When creating the schematic, you could always use U1a for every 2-input NAND gate. Right before the netlist is created, a “Packager” is run that stuffs all of the individual gates into groups of four to fill up the physical chip. Then, when autoplacing the components, it places the chips as close as it can. Then, you ran a “gate” optimization which would swap out gates between chips to make the optimization better. Finally, you would do a pin optimization to possibly swap the pins on an individual gate. After all the optimization was done, the layout program could back-annotate the schematic to keep everything in sync.