Currently i get a ERC error (roughly translated to):
pins of type data out and power out are connected
More specifically, I’ve connected an IC logic level input to the +5V net, in order to maintan the input pin constantly high. Besides this, I am using the PWR_FLAG symbol accordingly in my schematics, and it passes the ERC test.
Not sure how to resolve this, as I prefer to clear all ERC’s that comes up. Any ideas?
The ERC-error-message says that you connected a “DATA OUT” to a “POWER OUT” pin. To outputs connected together are normally not a good idea (hence the ERC-error).
The power-out is probably the PWR_FLAG_symbol. (which is ok).
So remains the “data out”-pin:
Either your “input”-pin is falsely declared as “data out” in the symbol definition. (error in library).
Or it is in fact not a input, but really an output pin. In this case it’s a wiring-error and the ERC has proven it’s usefulness.
IO Pads contain a PNPN structure that is a Silicon Controlled Rectifier between Power and ground with the IO pad connected to the trigger. That means if you ever raise a logic input to a voltage greater than the supply voltage then this SCR will fire and draw lots of current. This is known as Latch Up.
This can happen if you tie an input directly to the supply voltage. If the path to the pin is faster than the path to the supply then the pin can see a higher voltage during power up. Using a pull up prevents this.
The error is unambiguous. There’s an error in either the schematic or the library.
The hypothesis about inputs and power supply may apply to 60-year old 74xx parts (and I even doubt that).
Connecting an input directly to a VDD pin can only cause a delay of 2 cm of track maximum and is standard practice. Who wants to plaster resistors all over the place when it’s unnecessary?
I can imagine it only if the input is connected directly to VCC source and IC VCC pin is driven by ferrite bead (or other supply filter). It is wrong connection in my opinion so I assume that if IC is powered by ferrite bead than if any its input has to be set to ‘1’ than it will be connected directly to IC VCC pin and I don’t assume higher voltage at input than at supply pin.
If there is no ferrite bead used (and with wrong connection) than it is hardly (for me) to imagine enough energy pulse at input to Latch Up.
Writing that I all the time was thinking about a moment of power up (and assuming several uF at VCC source so rather slowly rising). But then I got an idea - what with ESD pulses near by such connection. And I think that ESD can really generate in such circuit (VCC pin connected to input pin) a pulse that may be will cause latch up and resistor in serie with input will limit such pulse current. That is new idea for me to consider ESD for such short connection, but it can be a source of problem.
I just assumed that in case of HC1G in SOT23-6 unused input set to ‘1’ can be connected with its VCC pin, but now I’m starting to doubt. So ‘a person learns all the life’
CMOS circuits are symmetrical, so the negative voltage at input relative to GND should also be a source of latch-up, but I suppose no one has anything against connecting input directly to GND???
But may be symmetry is less than I think…
You now need to update the symbol on your schematic to the new library symbol. (either by selecting the appropriate option or simply be deleting it and adding a new symbol from the library browser).
This is probably just different philosophies. A tiny SMD resistor costs next to nothing (if not really nothing, some fabricators don’t charge for common SMD parts) and reserving a space for it might be useful if something goes wrong or for debugging purposes. An SMD resistor can also cross some other tracks, which might be useful even if you don’t really need the resistance.
But if the voltage doesn’t go above VDD, you should be fine here even without a resistor.