5.99 Trying to understand ERC errors

Application: KiCad Schematic Editor

Version: 5.99.0-unknown-0cdffa16d4~142~ubuntu20.04.1, release build

Libraries:
	wxWidgets 3.0.4
	libcurl/7.68.0 OpenSSL/1.1.1f zlib/1.2.11 brotli/1.0.7 libidn2/2.2.0 libpsl/0.21.0 (+libidn2/2.2.0) libssh/0.9.3/openssl/zlib nghttp2/1.40.0 librtmp/2.3

Platform: Linux 5.11.0-37-generic x86_64, 64 bit, Little endian, wxGTK, ubuntu, x11

Build Info:
	Date: Oct 28 2021 22:28:00
	wxWidgets: 3.0.4 (wchar_t,wx containers,compatible with 2.8) GTK+ 3.24
	Boost: 1.71.0
	OCC: 7.5.2
	Curl: 7.68.0
	ngspice: 31
	Compiler: GCC 9.3.0 with C++ ABI 1013

Build settings:
	KICAD_USE_OCC=ON
	KICAD_SPICE=ON

Iā€™ve been using 5.1.x for a while now and have just installed 5.99 so I can get familiar with it in time for release.

Opened up a schematic which has now been converted to 5.99 format. When I run ERC I get a pile of error which I canā€™t wrap my head around.

Most of the errors are net not bus member errors:

[net_not_bus_member]: Net /D4 is graphically connected to bus /<NO NET> but is not a member of that bus
    ; Severity: warning
    @(215.26 mm, 74.93 mm): Bus to Wire Entry
    @(215.26 mm, 30.48 mm): Vertical Bus, length 52.07 mm

There are also some warnings about library files being modified:

[lib_symbol_issues]: Symbol 'ATtiny85-20SU' has been modified in library 'MCU_Microchip_ATtiny'.
    ; Severity: warning
    @(55.24 mm, 160.66 mm): Symbol U1 [ATtiny85-20SU]

Is this something I should be concerned about and I need to fix?

I can upload the project if required.

Full error list here: https://pastebin.com/0tpSyZnz

The first is complaining that the wires you have connected to the bus arenā€™t in the bus definition. Do you have a label on the bus? If not, youā€™ll get this error (although perhaps we should suppress it if thereā€™s no label at all). Alternatively you might have a label that isnā€™t in the correct format. If you right-click on the bus and select the Bus Unfold option it should show you what it thinks is in the bus.

The second one is saying that the copy of ATtiny85-20SU in the library is different from the one on the board. That might be OK, or it might mean that you made a change to it in the library and havenā€™t yet updated it on the board.

Thanks. I donā€™t have a label on the bus. Iā€™ve never set this on 5.1.x so guess this is something new for 5.99. Will look into bus labels.

Iā€™ve made no changes to the ATtiny symbol. Is this saying the symbol from the 5.1 version is different to the symbol in the library on 5.99?

Update: Iā€™ve removed and replaced the symbol and the error has now gone (Symbol looks the same)

You donā€™t have to label your buses, although it provides extra checking if you do. If you donā€™t, you can right click on the error message in the ERC window and chose ā€œIgnore all xxx violationsā€.

(You can edit all the violation severity settings in the Schematic Setup dialog.)

I might as well get used to labeling the buses. As you said it provides extra protection so this is a good idea.

Iā€™ve managed to fix the bus errors by giving them a label, but have had to do a hack in that I cannot have a single bus containing address lines and data lines. So for example, the address bus is as below, and then I have a similar one for databus.

Is it possible to have a single bus for data and address line and use the labeling as D[0ā€¦7], A[0-12]
(That doesnā€™t work so maybe I just have the formatting incorrect?)

Now you can in 5.99: {D[0..7] A[0..12]}

Tried that but no luck.

Label: A[0ā€¦12] D[0ā€¦7]
I get signal name contains ā€˜[ā€™ or ā€˜]ā€™ but is not a valid bus name.

Use two dots in a row, not three.

Two dots, but also you missed the curly braces around it all. The curly braces are what defines a group bus, which is a new concept in 5.99 that allows multiple different net names in one bus.

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Perfect. That did it - missed the curly brackets (extra dot was a typo)

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