I have a hierarchical design with over 60 sheets. I’m using the bus definitions to group large amounts of single signals and connect different sheets in the root sheet. This way I get a block diagram of the design on the first sheet. Maybe this isn’t how the busses are intended to work in KiCad, because I found a problem with the ERC.
My expectation was that each signal in a bus has to occur at least two times in a design, else the ERC would report an unconnected net. But this seems not to be the case. I tried it in a simple design, where I connected two sheets with a bus and on SheetB I removed one signal. The ERC reports no error.
Is this intended?
The only solution to find such errors right now is to use the Net Inspector from the PCB and sort for pads. Then I check all nets which are only connected to one pad. But most times these are the pads marked as unconnected.
k599_test.zip (10.5 KB)
Application: KiCad Schematic Editor (64-bit) Version: (5.99.0-12680-geb819a3b25), release build Libraries: wxWidgets 3.1.5 libcurl/7.78.0-DEV Schannel zlib/1.2.11 Platform: Windows 10 (build 19042), 64-bit edition, 64 bit, Little endian, wxMSW Build Info: Date: Oct 4 2021 21:01:04 wxWidgets: 3.1.5 (wchar_t,wx containers) Boost: 1.76.0 OCC: 7.5.0 Curl: 7.78.0-DEV ngspice: 35 Compiler: Visual C++ 1929 without C++ ABI Build settings: KICAD_USE_OCC=ON KICAD_SPICE=ON